Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

2007 ◽  
Vol 47 (6) ◽  
pp. 937-943 ◽  
Author(s):  
W.B. Chen ◽  
J.P. Xu ◽  
P.T. Lai ◽  
Y.P. Li ◽  
S.G. Xu
2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.


2011 ◽  
Vol 88 (7) ◽  
pp. 1309-1311 ◽  
Author(s):  
C.H. Fu ◽  
K.S. Chang-Liao ◽  
Y.A. Chang ◽  
Y.Y. Hsu ◽  
T.H. Tzeng ◽  
...  

2019 ◽  
Vol 2 (1) ◽  
pp. 41-48
Author(s):  
Rosa María Luna-Sánchez ◽  
Ignacio González-Martínez

2008 ◽  
Vol 85 (1) ◽  
pp. 20-26 ◽  
Author(s):  
Chun-Yuan Lu ◽  
Kuei-Shu Chang-Liao ◽  
Chun-Chang Lu ◽  
Ping-Hung Tsai ◽  
Yin Yin Kyi ◽  
...  

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