Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

2005 ◽  
Vol 77 (3-4) ◽  
pp. 292-296 ◽  
Author(s):  
Dongwoo Suh ◽  
Bongki Mheen
Keyword(s):  
Quality Factor ◽  
Current Path ◽  
Spiral Inductors ◽  
Parallel Current

Spiral Inductors with Multi-Strip Coils Processed on Sapphire and Bulk Silicon Substrates

2004 ◽  
Vol 1 (4) ◽  
pp. 206-216
Author(s):  
Päivi H. Karjalainen ◽  
Juha Rapelo ◽  
Eero O. Ristolainen
Keyword(s):  
Quality Factor ◽  
Element Model ◽  
Silicon Substrates ◽  
Lumped Element ◽  
Strip Layout ◽  
Determining Factors ◽  
Inductor Coil ◽  
Spiral Inductors ◽  
Lumped Element Model ◽  
Line Space

Improvements in inductor properties are demonstrated using inductors fabricated by the SOS and CMOS processes. Inductor coils are constructed in the form of several separate strips and the effect of the coil layout on the inductance and quality factor is examined with respect to traditional (“un-slit”) inductors. Optimized multi-strip layout increases the inductance and the quality factor of an inductor. The coil layout has very little influence on the self-resonance frequency of the inductor. Multi-strip layout of the inductor coil increases the coil's series resistance, which in conjunction with the proximity effect causes the critical frequency to increase. The number of slits, the spacing between coils, and the width of the slits are the determining factors for improving the inductor characteristics when using a multi-strip arrangement. The layout produces an improvement especially in the case of SOS inductors. A ladder-type lumped element model for multi-strip inductors is presented. (The words “strip/slit” are equivalent to “track/space” or “line/space”)

scholarly journals Design of a multilayer on-chip inductor by computational electromagnetic modelling

2019 ◽  
Vol 70 (5) ◽  
pp. 379-385
Author(s):  
Muneeswaran Dhamodaran ◽  
Subramani Jegadeesan ◽  
Arunachalam Murugan
Keyword(s):  
Quality Factor ◽  
Method Of Moments ◽  
Spiral Inductor ◽  
Electromagnetic Modeling ◽  
Technological Parameters ◽  
Full Field ◽  
Electromagnetic Model ◽  
Electromagnetic Modelling ◽  
Spiral Inductors ◽  
On Chip

Abstract This paper presents a design of typical multilayer on-chip inductor to determine the layout parameters of the desired inductance value of electromagnetic modeling. The inductance and quality factor of multilayer on-chip spiral inductors are determined by its layout parameters and technological parameters. These layout parameters must be optimized to obtain the maximum quality factor at the desired frequency of operation. An electromagnetic model with fewer assumptions than empirical equations and higher efficiency than full-field solvers would be welcome. So would facile comparisons of different inductor structures. This paper describes recent works on the electromagnetic modeling of on-chip inductor structures applied to the comparison of inductor geometries, including the traditional spiral inductor and a novel multilayer inductor. The electromagnetic modeling of the investigative model is presented. The modeling and simulation are implemented using the method of moments. To simulate the proposed algorithm, the EM Simulator software is used.

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