scholarly journals Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata

Data in Brief ◽  
2017 ◽  
Vol 10 ◽  
pp. 557-560 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Mohammad Maksudur Rahman ◽  
Nur Mohammad Nahid ◽  
Md. Kamrul Hassan
2013 ◽  
Vol 10 (10) ◽  
pp. 2347-2353 ◽  
Author(s):  
Samira Sayedsalehi ◽  
Mohammad Hossein Moaiyeri ◽  
Keivan Navi

2018 ◽  
Vol 7 (4) ◽  
pp. 2747
Author(s):  
C Santhi ◽  
Dr. Moparthy Gurunadha Babu

A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit. 


2018 ◽  
Vol 9 (4) ◽  
pp. 2641-2648 ◽  
Author(s):  
Md. Abdullah-Al-Shafi ◽  
Ali Newaz Bahar ◽  
Md. Ahsan Habib ◽  
Mohammad Maksudur Rahman Bhuiyan ◽  
Firdous Ahmad ◽  
...  

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