A Novel Method of Designing an all Optical 3-Bit Asynchronous Counter

In digital signal processing and data communication system in optical domain it is paramount important to count the pulse number of any device or processor and hence optical counter for fast counting. In this letter the authors propose a new method to implement an all-optical 3- bit asynchronous binary counter comprising all-optical T flip flops which works based on the polarization switching characteristics of SOA, and frequency encoded data have been used for communication purpose. Use of Frequency encoding technique in the proposed scheme makes it attractive and effective one in various aspects in wave division multiplexing based communication network. Simulation aided results support the practicability of the proposed scheme.

Fpga Implementation of Active Neighborhood Pattern Sensitive Fault Testing using Tiling Method

Test structure for Active Neighborhood Pattern Sensitive Fault (ANPSF) in memories with high switching speed is modeled in this paper. Algorithm for ANPSF testing is developed using type-1 neighborhood approach. The type-1 neighborhood, also known as tiling method has one victim and four aggressor cells. It is used to identify the ANPSF effect on base cell by the switching of patterns in the corresponding deleted neighborhood cells. The required test pattern can be generated using a Binary counter, Hamiltonian or Gray pattern generator where the two successive values differ in only one binary digit. The BIST architecture allows to incorporate the hardware required by the user to select the victim and corresponding aggressor cells to test the complete memory. It helps in application of test pattern for the memory circuit under test on user’s choice. The main objective of this model is to develop the architecture for tiling methodology with test pattern generator to detect the transitions in aggressor cells with edge detection technique. The proposed work enables to verify the response of victim cell which may cause a change in value resulting in an active neighborhood pattern sensitive fault scenario. The complete ANPSF model architecture for memory testing is developed using Verilog hardware descriptive language. The process of simulation and synthesis report is validated using Xilinx 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

High Performance of Wallace Tree Multiplier Stacking Circuit

In this paper one novel double counter proposed which is quick when contrasted with another normal's parallel counters. First, we are designing binary counter using solely full adders, and after with new symmetric stacking method. We are evaluating these two techniques and displaying how the symmetric stacking method is decreasing the x-or gate delays in the essential route of the binary counter. This kind of our proposed counter is very useful in the existing counter based totally Wallace tree multiplier design. With this new symmetry stacking counter we are lowering delay and increasing the performance of multipliers in VLSI circuits. We are designing and simulating our proposed quick binary counter using Xilinx ISE layout suite14.7.

Area efficient LFSR based ADC in 45nm Technology using verilog a

Data converters are very much useful in this modern world for circuit design at both ends i.e., transmitter end and receiver end. This paper primarily aims at reducing the overall area of the 8 bit ADC by decreasing the size of traditional counter with replacement of LFSR which uses few XOR gates and FFs. Another advantage of using LFSR is that it produce random states which may result in reducing the conversion time or in other words speeding up the ADC. Verilog A is used for implementing the ADC since it uses high level behavior model which allows to use simple equation to describe complex issues, a Standard language, Easy to learn and use and Flexible for both analog and AMS application Verilog A is much more simple than Spice C code. Linear feedback shift register is employed in the implementation of ADC as it fewer components than binary counter. The proposed ADC architecture is implemented and simulated using Cadence 0.45 µm tool and compared with Standard ADC which uses traditional binary counter. Results show that there is almost 50% in power savings when compared to the traditional ADC designs.