FPGA based Design of Triple Modular Redundancy for Hybrid Digital Pulse Width Modulation Generator

This paper proposes the Triple Modular Redundancy checker for the Hybrid Digital Pulse Width Modulation generator to verify the correctness in the output signal. The proposed design involves replicating the Hybrid Digital Pulse Width Modulation Generator thrice and the majority voter circuit validates the correct output by considering the two accurate signals out of the three outputs. The digital pulse width modulation generator is broadly classified as Counter-based Digital Pulse Width Modulation, Delay line-based Digital Pulse Width Modulation, and Hybrid-based Digital Pulse Width Modulation. Among the three methods, the Hybrid based Digital Pulse Width Modulation is preferred as the Counter-based Digital Pulse Width Modulation uses high clocking frequency and the Delay line-based Digital Pulse Width Modulation occupies a large area. The proposed Triple Modular Redundancy is implemented using the FPGA and parameters such as power analysis and device utilization chart.

Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR Implementation

This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology.

A Novel Scheme for Fault Tolerant Computing

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

Synthesis of composite logic gate in QCA embedding underlying regular clocking

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

Simulation of a tripled majority voter by Quartus Prime State Machine

A triple majority element based on a full adder in the Quartus Prime State Machine is investigated to create highly reliable FPGA-based digital automata. For this purpose, two new groups of inputs are added to the previously developed automaton graph. Modeling the failure of one of the three majorities is performed by specifying the corresponding constant in one of the three input groups. The performance indicators of the developed device are evaluated.