scholarly journals Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

Small ◽  
2020 ◽  
Vol 16 (47) ◽  
pp. 2004907
Author(s):  
Taro Sasaki ◽  
Keiji Ueno ◽  
Takashi Taniguchi ◽  
Kenji Watanabe ◽  
Tomonori Nishimura ◽  
...  
Keyword(s):  
Gate Voltage ◽  
2D Materials ◽  
Memory Window ◽  
Floating Gate ◽  
Memory Devices

Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory

ACS Nano ◽  
2021 ◽  
Vol 15 (4) ◽  
pp. 6658-6668
Author(s):  
Taro Sasaki ◽  
Keiji Ueno ◽  
Takashi Taniguchi ◽  
Kenji Watanabe ◽  
Tomonori Nishimura ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Floating Gate ◽  
Memory Devices ◽  
Device Structure

Semiconductor Nanocrystal Floating-gate Memory Devices

2004 ◽  
Vol 830 ◽  
Author(s):  
P. Dimitrakis ◽  
P. Normand
Keyword(s):  
Low Voltage ◽  
Ion Beam ◽  
Low Energy ◽  
Floating Gate ◽  
Device Performance ◽  
Memory Devices ◽  
Research Directions ◽  
Semiconductor Nanocrystal ◽  
Floating Gate Memory ◽  
Attractive Option

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

scholarly journals Temperature-Dependent Physical and Memory Characteristics of Atomic-Layer-DepositedRuOxMetal Nanocrystal Capacitors

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
S. Maikap ◽  
W. Banerjee ◽  
T. C. Tien ◽  
T. Y. Wang ◽  
J. R. Yang
Keyword(s):  
Gate Voltage ◽  
Annealing Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Memory Window ◽  
Silicate Layer ◽  
Metal Nanocrystals ◽  
Annealing Temperatures ◽  
Memory Characteristics

Physical and memory characteristics of the atomic-layer-depositedRuOxmetal nanocrystal capacitors in an n-Si/SiO2/HfO2/RuOx/Al2O3/Pt structure with different postdeposition annealing temperatures from 850–1000°C have been investigated. TheRuOxmetal nanocrystals with an average diameter of 7 nm and a highdensity of 0.7 × 1012/cm2are observed by high-resolution transmission electron microscopy after a postdeposition annealing temperature at 1000°C. The density ofRuOxnanocrystal is decreased (slightly) by increasing the annealing temperatures, due to agglomeration of multiple nanocrystals. The RuO3nanocrystals and Hf-silicate layer at the SiO2/HfO2interface are confirmed by X-ray photoelectron spectroscopy. For post-deposition annealing temperature of 1000°C, the memory capacitors with a small equivalent oxide thickness of ~9 nm possess a large hysteresis memory window of >5 V at a small sweeping gate voltage of ±5 V. A promising memory window under a small sweeping gate voltage of ~3 V is also observed due to charge trapping in theRuOxmetal nanocrystals. The program/erase mechanism is modified Fowler-Nordheim (F-N) tunneling of the electrons and holes from Si substrate. The electrons and holes are trapped in theRuOxnanocrystals. Excellent program/erase endurance of 106cycles and a large memory window of 4.3 V with a small charge loss of ~23% at 85°C are observed after 10 years of data retention time, due to the deep-level traps in theRuOxnanocrystals. The memory structure is very promising for future nanoscale nonvolatile memory applications.

A Floating Gate and Its Application to Memory Devices

1967 ◽  
Vol 46 (6) ◽  
pp. 1288-1295 ◽  
Author(s):  
D. Kahng ◽  
S. M. Sze
Keyword(s):  
Floating Gate ◽  
Memory Devices

Fabrication of Arrayed Si Nanowire-Based Nano-Floating Gate Memory Devices on Flexible Plastics

2012 ◽  
Vol 12 (1) ◽  
pp. 578-584
Author(s):  
Changjoon Yoon ◽  
Youngin Jeon ◽  
Junggwon Yun ◽  
Sangsig Kim
Keyword(s):  
Floating Gate ◽  
Memory Devices ◽  
Si Nanowire ◽  
Floating Gate Memory

Electrical Characteristics of Floating-Gate Memory Devices with Titanium Nanoparticles Embedded in Gate Oxides

2009 ◽  
Vol 9 (3) ◽  
pp. 1904-1908 ◽  
Author(s):  
Byoungjun Park ◽  
Kyoungah Cho ◽  
Junggwon Yun ◽  
Yong-Seo Koo ◽  
Jong-Ho Lee ◽  
...  
Keyword(s):  
Floating Gate ◽  
Memory Devices ◽  
Electrical Characteristics ◽  
Gate Oxides ◽  
Floating Gate Memory ◽  
Titanium Nanoparticles

Nano-Floating Gate Memory Devices with Metal-Oxide Nanoparticles in Polyimide Dielectrics

2008 ◽  
Vol 8 (1) ◽  
pp. 21-26 ◽  
Author(s):  
Eun-Kyu Kim ◽  
Dong-Uk Lee ◽  
Seon-Pil Kim ◽  
Tae-Hee Lee ◽  
Hyun-Mo Koo ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Nanoparticles ◽  
Floating Gate ◽  
Oxide Nanoparticles ◽  
Memory Devices ◽  
Floating Gate Memory
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