2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
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Published By IEEE

9781424416141

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Future memory technology: challenges and opportunities

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530774 ◽

2008 ◽

Cited By ~ 39

Author(s):

Kinam Kim

Keyword(s):

Challenges And Opportunities

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Achieving Low Vt (≪-0.3V) and Thin EOT (~1.0nm) in Gate First Metal/High-k pMOSFET for High Performance CMOS Applications

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530843 ◽

2008 ◽

Author(s):

C. S. Park ◽

G. Bersuker ◽

S. C. Song ◽

H. B. Park ◽

C. Burham ◽

...

Keyword(s):

High Performance ◽

High K

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The Ballistic Transport and Reliability of the SOI and Strained-SOI nMOSFETs with 65nm Node and Beyond Technology

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530826 ◽

2008 ◽

Author(s):

E. R. Hsieh ◽

Derrick W. Chang ◽

S. S. Chung ◽

Y. H. Lin ◽

C. H. Tsai ◽

...

Keyword(s):

Ballistic Transport

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Temporal Changes of Parameters in Phase Change Memory

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530836 ◽

2008 ◽

Cited By ~ 1

Author(s):

I. Karpov ◽

M. Mitra ◽

D. Kau ◽

G. Spadini ◽

Y. A. Kryukov ◽

...

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Temporal Changes ◽

Change Memory

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Low-Leakage SMARTMOS¿ 10W Technology At 0.13¿m Node with Optimized Analog, Power and Logic Devices for SOC Design

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530822 ◽

2008 ◽

Cited By ~ 1

Author(s):

Hongning Yang ◽

Won-Gi Min ◽

Xin Lin ◽

Veronique Newenhouse ◽

John Huber ◽

...

Keyword(s):

Logic Devices ◽

Low Leakage

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Performance and leakage optimization in carbon and fluorine co-implanted pMOSFETs

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530784 ◽

2008 ◽

Author(s):

B.J. Pawlak ◽

R. Duffy ◽

J.C. Hooker ◽

T. Hoffman ◽

S. B. Felch ◽

...

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Periphery Scaling Challenges for NVM

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530791 ◽

2008 ◽

Author(s):

Adam Brand ◽

Ranadeep Dutta ◽

Sean Ma ◽

Robi Banerjee

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Integrated Micromechanical Radio Front-Ends

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530773 ◽

2008 ◽

Cited By ~ 13

Author(s):

Clark T.-C. Nguyen

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Cell Design Considerations for Phase Change Memory as a Universal Memory

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530832 ◽

2008 ◽

Cited By ~ 12

Author(s):

Chung Lam

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Cell Design ◽

Design Considerations ◽

Change Memory

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Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2008.4530842 ◽

2008 ◽

Cited By ~ 1

Author(s):

J. Huang ◽

P. D. Kirsch ◽

M. Hussain ◽

D. Heh ◽

P. Sivasubramani ◽

...

Keyword(s):

Band Edge ◽

High K

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2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Future memory technology: challenges and opportunities

Achieving Low Vt (≪-0.3V) and Thin EOT (~1.0nm) in Gate First Metal/High-k pMOSFET for High Performance CMOS Applications

The Ballistic Transport and Reliability of the SOI and Strained-SOI nMOSFETs with 65nm Node and Beyond Technology

Temporal Changes of Parameters in Phase Change Memory

Low-Leakage SMARTMOS¿ 10W Technology At 0.13¿m Node with Optimized Analog, Power and Logic Devices for SOC Design

Performance and leakage optimization in carbon and fluorine co-implanted pMOSFETs

Periphery Scaling Challenges for NVM

Integrated Micromechanical Radio Front-Ends

Cell Design Considerations for Phase Change Memory as a Universal Memory

Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Latest Publications