scholarly journals Temperature-Dependent Physical and Memory Characteristics of Atomic-Layer-DepositedRuOxMetal Nanocrystal Capacitors

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
S. Maikap ◽  
W. Banerjee ◽  
T. C. Tien ◽  
T. Y. Wang ◽  
J. R. Yang
Keyword(s):  
Gate Voltage ◽  
Annealing Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Memory Window ◽  
Silicate Layer ◽  
Metal Nanocrystals ◽  
Annealing Temperatures ◽  
Memory Characteristics

Physical and memory characteristics of the atomic-layer-depositedRuOxmetal nanocrystal capacitors in an n-Si/SiO2/HfO2/RuOx/Al2O3/Pt structure with different postdeposition annealing temperatures from 850–1000°C have been investigated. TheRuOxmetal nanocrystals with an average diameter of 7 nm and a highdensity of 0.7 × 1012/cm2are observed by high-resolution transmission electron microscopy after a postdeposition annealing temperature at 1000°C. The density ofRuOxnanocrystal is decreased (slightly) by increasing the annealing temperatures, due to agglomeration of multiple nanocrystals. The RuO3nanocrystals and Hf-silicate layer at the SiO2/HfO2interface are confirmed by X-ray photoelectron spectroscopy. For post-deposition annealing temperature of 1000°C, the memory capacitors with a small equivalent oxide thickness of ~9 nm possess a large hysteresis memory window of >5 V at a small sweeping gate voltage of ±5 V. A promising memory window under a small sweeping gate voltage of ~3 V is also observed due to charge trapping in theRuOxmetal nanocrystals. The program/erase mechanism is modified Fowler-Nordheim (F-N) tunneling of the electrons and holes from Si substrate. The electrons and holes are trapped in theRuOxnanocrystals. Excellent program/erase endurance of 106cycles and a large memory window of 4.3 V with a small charge loss of ~23% at 85°C are observed after 10 years of data retention time, due to the deep-level traps in theRuOxnanocrystals. The memory structure is very promising for future nanoscale nonvolatile memory applications.

Electrical Properties of Srta2O6 Thin Films Deposited by Plasma Enhanced Atomic Layer Deposition (Peald)

2001 ◽  
Vol 685 ◽  
Author(s):  
Won-Jae Lee ◽  
Chang-Ho Shin ◽  
In-Kyu You ◽  
Il-Suk Yang ◽  
Sang-Ouk Ryu ◽  
...  
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Atomic Layer Deposition ◽  
Leakage Current ◽  
Annealing Temperature ◽  
Atomic Layer ◽  
Si Substrates ◽  
Annealing Temperatures ◽  
Layer Deposition ◽  
Current Characteristics

AbstractThe SrTa2O6 (STO) thin films were prepared by plasma enhanced atomic layer deposition (PEALD) with alternating supply of reactant sources, Sr[Ta(C2H5O)5(C4H10NO)]2 {Strontium bis-[tantalum penta-ethoxide dimethyllaminoethoxide]; Sr(Ta(OEt)5▪dmae)2} and O2plasma. It was observed that the uniform and conformal STO thin films were successfully deposited using PEALD and the film thickness per cycle was saturated at about 0.8 nm at 300°C. Electrical properties of SrTa2O6 (STO) thin films prepared on Pt/SiO2/Si substrates with annealing temperatures have been investigated. While the grain size and dielectric constant of STO films increased with increasing annealing temperature, the leakage current characteristics of STO films slightly deteriorated. The leakage current density of a 40nm-STO film was about 5×10−8A/cm2 at 3V.

scholarly journals Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Dan-Dan Liu ◽  
Wen-Jun Liu ◽  
Jun-Xiang Pei ◽  
Lin-Yan Xie ◽  
Jingyong Huo ◽  
...  
Keyword(s):  
Thin Film ◽  
Oxygen Vacancy ◽  
Gate Voltage ◽  
Oxygen Vacancies ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Gate Bias ◽  
Voltage Polarity ◽  
Bias Pulse

AbstractAmorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO+) and doubly ionized oxygen vacancy (VO2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.

Charge Trapping Memories With Atomic Layer Deposited High-k Dielectrics Capping Layers

2010 ◽  
Vol 1250 ◽  
Author(s):  
Nikolaos Nikolaou ◽  
Panos Dimitrakis ◽  
Pascal Normand ◽  
Konstantinos Giannakopoulos ◽  
Konstantina Mergia ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Atomic Layer ◽  
Dielectric Strength ◽  
Precursor Chemistry ◽  
Memory Window ◽  
Trapping Efficiency ◽  
Zirconium Oxides ◽  
Metal Precursors ◽  
High K ◽  
Memory Structures

AbstractIn this work, we examine the influence of hafnium and zirconium oxides ALD precursor chemistry on the memory properties of SiO2/Si3N4/ZrO2 and SiO2/Si3N4/HfO2 non-volatile gate memory stacks. Approximately 10 nm thick ZrO2 and HfO2 layers were deposited on top of a SiO2/Si3N4 structure, functioning as blocking oxides. Both metal oxides were deposited using either alkylamides or cyclopentadienyls as metal precursors, and ozone as the oxygen source. In the case of the ZrO2 gate stacks a memory window of 6 V was determined, comprised of 4 V write window and 2 V erase window. Although no dramatic differences were evident between the ZrO2 layers, ZrO2 grown from alkylamide provided structures with higher dielectric strength. The memory structures with HfO2 blocking layers indicate that the memory window and the dielectric strength are significantly affected by the precursor. The structures with the HfO2 formed from alkylamide showed a write window of 7 V, while the films grown from cyclopentadienyl possessed window of 5 V. Comparison between the memory windows obtained using ZrO2 and HfO2 as control oxides reveals that the former provides memory structures with higher electron trapping efficiency.

Outstanding memory characteristics with atomic layer deposited Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 nanocomposite structures as the charge trapping layer

2019 ◽  
Vol 467-468 ◽  
pp. 423-427 ◽  
Author(s):  
Ping Han ◽  
Tian-Cheng Lai ◽  
Mei Wang ◽  
Xi-Rui Zhao ◽  
Yan-Qiang Cao ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Atomic Layer ◽  
Memory Characteristics ◽  
Nanocomposite Structures

scholarly journals Structural and Optical Characterization of ZnS Ultrathin Films Prepared by Low-Temperature ALD from Diethylzinc and 1.5-Pentanedithiol after Various Annealing Treatments

Materials ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3212 ◽  
Author(s):  
Maksymilian Włodarski ◽  
Urszula Chodorow ◽  
Stanisław Jóźwiak ◽  
Matti Putkonen ◽  
Tomasz Durejko ◽  
...  
Keyword(s):  
Low Temperature ◽  
Ultrathin Films ◽  
Quantum Confinement ◽  
Annealing Temperature ◽  
Atomic Layer ◽  
Sphalerite Structure ◽  
Annealing Temperatures ◽  
Annealing Conditions ◽  
Layer Deposition

The structural and optical evolution of the ZnS thin films prepared by atomic layer deposition (ALD) from the diethylzinc (DEZ) and 1,5-pentanedithiol (PDT) as zinc and sulfur precursors was studied. A deposited ZnS layer (of about 60 nm) is amorphous, with a significant S excess. After annealing, the stoichiometry improved for annealing temperatures ≥400 °C and annealing time ≥2 h, and 1:1 stoichiometry was obtained when annealed at 500 °C for 4 h. ZnS crystallized into small crystallites (1–7 nm) with cubic sphalerite structure, which remained stable under the applied annealing conditions. The size of the crystallites (D) tended to decrease with annealing temperature, in agreement with the EDS data (decreased content of both S and Zn with annealing temperature); the D for samples annealed at 600 °C (for the time ≤2 h) was always the smallest. Both reflectivity and ellipsometric spectra showed characteristics typical for quantum confinement (distinct dips/peaks in UV spectral region). It can thus be concluded that the amorphous ZnS layer obtained at a relatively low temperature (150 °C) from organic S precursor transformed into the layers built of small ZnS nanocrystals of cubic structure after annealing at a temperature range of 300–600 °C under Ar atmosphere.

scholarly journals The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 784 ◽  
Author(s):  
Joong-Hyun Park ◽  
Myung-Hun Shin ◽  
Jun-Sin Yi
Keyword(s):  
Zinc Oxide ◽  
Gate Voltage ◽  
Voltage Pulse ◽  
Charge Trapping ◽  
Memory Window ◽  
Logic Devices ◽  
Non Volatile Memory ◽  
Sweep Voltage ◽  
Mis Capacitors ◽  
Bottom Gate

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Improvement of the Specific Contact Resistance on P-Type 4H-SiC by Using a Highly P-Typed Doped 4H-SiC Layer Selectively Grown by VLS Transport

2014 ◽  
Vol 806 ◽  
pp. 57-60
Author(s):  
Nicolas Thierry-Jebali ◽  
Arthur Vo-Ha ◽  
Davy Carole ◽  
Mihai Lazar ◽  
Gabriel Ferro ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Ohmic Contacts ◽  
Schottky Barrier Height ◽  
Annealing Temperature ◽  
Process Condition ◽  
Specific Contact Resistance ◽  
High Doping Level ◽  
Annealing Temperatures ◽  
Specific Contact ◽  
P Type

This work reports on the improvement of ohmic contacts made on heavily p-type doped 4H-SiC epitaxial layer selectively grown by Vapor-Liquid-Solid (VLS) transport. Even before any annealing process, the contact is ohmic. This behavior can be explained by the high doping level of the VLS layer (Al concentration > 1020 cm-3) as characterized by SIMS profiling. Upon variation of annealing temperatures, a minimum value of the Specific Contact Resistance (SCR) down to 1.3x10-6 Ω.cm2 has been obtained for both 500 °C and 800 °C annealing temperature. However, a large variation of the SCR was observed for a same process condition. This variation is mainly attributed to a variation of the Schottky Barrier Height.

Structural Changes of UHV Deposited Titanium Thin Films in Presence of Oxygen Flow and Temperature

2011 ◽  
Vol 110-116 ◽  
pp. 1094-1098
Author(s):  
Haleh Kangarlou ◽  
Mehdi Bahrami Gharahasanloo ◽  
Akbar Abdi Saray ◽  
Reza Mohammadi Gharabagh
Keyword(s):  
Room Temperature ◽  
Structural Changes ◽  
Annealing Temperature ◽  
Annealing Process ◽  
Oxygen Flow ◽  
Glass Substrates ◽  
Annealing Temperatures ◽  
Titanium Thin Films ◽  
Deposition Angle ◽  
Ti Films

Ti films of same thickness, and near normal deposition angle, and same deposition rate were deposited on glass substrates, at room temperature, under UHV conditions. Different annealing temperatures as 393K, 493K and 593K with uniform 8 cm3/sec, oxygen flow, were used for producing titanium oxide layers. Their nanostructures were determined by AFM and XRD methods. Roughness of the films changed due to annealing process. The gettering property of Ti and annealing temperature can play an important role in the nanostructure of the films.

scholarly journals Experimental Investigation on Micro Deep Drawing of Stainless Steel Foils with Different Microstructural Characteristics

2021 ◽  
Vol 34 (1) ◽  
Author(s):  
Jingwei Zhao ◽  
Tao Wang ◽  
Fanghui Jia ◽  
Zhou Li ◽  
Cunlong Zhou ◽  
...  
Keyword(s):  
Stainless Steel ◽  
Deep Drawing ◽  
Annealing Temperature ◽  
Localized Deformation ◽  
Microstructural Characteristics ◽  
Height Profile ◽  
Annealing Temperatures ◽  
Micro Deep Drawing ◽  
Profile Distribution

AbstractIn the present work, austenitic stainless steel (ASS) 304 foils with a thickness of 50 µm were first annealed at temperatures ranging from 700 to 1100 ℃ for 1 h to obtain different microstructural characteristics. Then the effects of microstructural characteristics on the formability of ASS 304 foils and the quality of drawn cups using micro deep drawing (MDD) were studied, and the mechanism involved was discussed. The results show that the as-received ASS 304 foil has a poor formability and cannot be used to form a cup using MDD. Serious wrinkling problem occurs on the drawn cup, and the height profile distribution on the mouth and the symmetry of the drawn cup is quite non-uniform when the annealing temperature is 700 ℃. At annealing temperatures of 900 and 950 ℃, the drawn cups are both characterized with very few wrinkles, and the distribution of height profile, symmetry and mouth thickness are uniform on the mouths of the drawn cups. The wrinkling becomes increasingly significant with a further increase of annealing temperature from 950 to 1100 ℃. The optimal annealing temperatures obtained in this study are 900 and 950 ℃ for reducing the generation of wrinkling, and therefore improving the quality of drawn cups. With non-optimized microstructure, the distribution of the compressive stress in the circumferential direction of the drawn foils becomes inhomogeneous, which is thought to be the cause of the occurrence of localized deformation till wrinkling during MDD.

Effect of Intercritical Annealing Temperature on Development of Cold Rolled Dual Phase Steel from Q345 Steel

2013 ◽  
Vol 313-314 ◽  
pp. 693-696
Author(s):  
Ji Yuan Liu ◽  
Fu Xian Zhu ◽  
Shi Cheng Ma
Keyword(s):  
Dual Phase Steel ◽  
Annealing Temperature ◽  
Simulation Experiment ◽  
Intercritical Annealing ◽  
Continuous Annealing ◽  
Dual Phase ◽  
Automotive Applications ◽  
Treatment Procedure ◽  
Annealing Temperatures ◽  
Cold Rolled

Cold rolled dual phase steel was developed from Q345 steel by heat treatment procedure for automotive applications. The ultimate tensile strength was improved about 100MPa higher than the traditional cold-rolled Q345 steel in the continuous annealing simulation experiment. The microstructure presented varied characteristics in different intercritical annealing temperatures; mechanical properties were changed correspondingly as well. The chief discussions are focus on the recrystallization, hardenability of austenite and martensite transformation in the experiment.

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