Packaging Parameters Analysis for the Fatigue Reliability of Stacked Chip Ball Grid Array by Using the Optimal Equivalent Solder Balls

2013 ◽  
Vol 31 (4) ◽  
pp. 543-566 ◽  
Author(s):  
Hsin-En Cheng ◽  
Rong-Sheng Chen ◽  
Chao-Yang Mao
Keyword(s):  
Ball Grid Array ◽  
Fatigue Reliability ◽  
Solder Balls ◽  
Parameters Analysis

A 10 MHz to 80 GHz BGA Transition from Chip to LTCC Interposer for Chip Scale Packages

2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000067-000072
Author(s):  
Bradley A. Thrasher ◽  
William E. McKinzie ◽  
Deepukumar M. Nair ◽  
Michael A. Smith ◽  
Allan Beikmohamadi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Electrical Performance ◽  
60 Ghz ◽  
Test Chip ◽  
Full Wave ◽  
Test Board ◽  
Measurement Results ◽  
Solder Balls

Presented here are the design, fabrication, and measurement results of a low temperature cofired ceramic (LTCC) chip-to-interposer transition utilizing a flip-chip ball grid array (BGA) interconnect that provides excellent electrical performance up to and including 80 GHz. A test board fabricated in LTCC is used as the interposer substrate and another smaller LTCC part is used as a surrogate chip for demonstration purposes. The BGA chip-to-interposer transition is designed as a back-to-back pair of transitions with an assembly consisting of an LTCC interposer, an LTCC test chip, and a BGA interconnect constructed with 260 μm diameter polymer core solder balls. The LTCC material employed is DuPont™ GreenTape™ 9K7. Full-wave simulation results predict excellent electrical performance from 10 MHz to 80 GHz, with the chip-to-interposer BGA transition having less than 0.5 dB insertion loss at 60 GHz and less than 1 dB insertion loss up to 80 GHz. In an assembled package (back-to-back BGA transitions), the insertion loss was measured to be 1 dB per transition at 60 GHz and less than 2 dB per transition for all frequencies up to 80 GHz.

Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000112-000116
Author(s):  
Joelle Arnold ◽  
Steph Gulbrandsen ◽  
Nathan Blattau
Keyword(s):  
Computer Tomography ◽  
Damage Accumulation ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Acoustic Microscopy ◽  
Eutectic Solder ◽  
X Ray ◽  
Area Array ◽  
Solder Balls ◽  
Commercial Off The Shelf

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.

Robust Design Optimization of Ball Grid Array Packaging

2011 ◽  
Author(s):  
Jae Chang Kim ◽  
Joo-Ho Choi ◽  
Yeong K. Kim
Keyword(s):  
Design Optimization ◽  
Robust Design ◽  
Strain Energy ◽  
Reduction Method ◽  
Ball Grid Array ◽  
Robust Design Optimization ◽  
Molding Compound ◽  
Materials Modeling ◽  
Solder Balls ◽  
Input Variables

In this paper, comparisons of the design optimization of ball grid array packaging geometry based on the elastic and viscoelastic material properties are made. Six geometric dimensions of the packaging are chosen as input variables. Molding compound and substrate are modeled as elastic and viscoelastic, respectively. Viscoplastic finite element analyses are performed to calculate the strain energy densities (SED) of the eutectic solder balls. Robust design optimizations to minimize SED are carried out, which accounts for the variance of the parameters via Kriging dimension reduction method. Optimum solutions are compared with those by the Taguchi method. It is found that the effects of the packaging geometry on the solder ball reliability are significant, and the optimization results are different depending on the materials modeling.

Electrical resistance of Sn–Ag–Cu ball grid array packages with Sn–Zn–Bi addition jointed at 240 °C

2007 ◽  
Vol 22 (1) ◽  
pp. 113-123
Author(s):  
Po-Cheng Shih ◽  
Kwang-Lung Lin
Keyword(s):  
Control System ◽  
Intermetallic Compound ◽  
Aging Time ◽  
Electrical Resistance ◽  
Ball Grid Array ◽  
Solder Paste ◽  
Solder Balls ◽  
Solder Bulk ◽  
Ball Grid Array Packages

Sn–8Zn–3Bi solder paste and Sn–3.2Ag–0.5Cu solder balls were reflowed simultaneously at 240 °C on Cu/Ni/Au metallized ball grid array substrates. The joints without Sn–Zn–Bi addition (only Sn–Ag–Cu) were studied as a control system. Electrical resistance was measured after multiple reflows and aging. The electrical resistance of the joint (R1) consisted of three parts: the solder bulk (Rsolder bulk, upper solder highly beyond the mask), interfacial solder/intermetallic compound (Rsolder/IMC), and the substrate (Rsubstrate). R1 increased with reflows and aging time. Rsolder/IMC, rather than Rsolder bulk and Rsubstrate, seemed to increase with reflows and aging time. The increase of R1 was ascribed to the Rsolder/IMC rises. Rsubstrate was the major contribution to R1. However Rsolder/IMC dominated the increase of R1 with reflows and aging. R1 of Sn–Zn–Bi/Sn–Ag–Cu samples were higher than that of Sn–Ag–Cu samples in various tests.

Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array

2004 ◽  
Vol 126 (4) ◽  
pp. 560-564 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Jenq-Dah Wu
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Thermomechanical Properties ◽  
Creep Model ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Dimensional Finite Element ◽  
Real Behavior ◽  
Thermal Cycling Fatigue

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.

Lead-free ceramic ball grid array: Thermomechanical fatigue reliability

2003 ◽  
Vol 32 (12) ◽  
pp. 1421-1425 ◽  
Author(s):  
Mukta Farooq ◽  
Charles Goldsmith ◽  
Ray Jackson ◽  
Gregory Martin
Keyword(s):  
Ball Grid Array ◽  
Thermomechanical Fatigue ◽  
Lead Free ◽  
Fatigue Reliability ◽  
Ceramic Ball ◽  
Lead Free Ceramic

BGA Solder Life Prediction under Combined Power and Temperature Cycling Condition

2012 ◽  
Vol 2012 (1) ◽  
pp. 000531-000534 ◽  
Author(s):  
Fei Chai ◽  
Michael Osterman ◽  
Michael Pecht
Keyword(s):  
Ball Grid Array ◽  
Temperature Cycling ◽  
Temperature Cycle ◽  
Fatigue Reliability ◽  
Sac305 Solder ◽  
Cycling Test ◽  
Solder Interconnect ◽  
Power Cycling ◽  
Plastic Ball ◽  
Plastic Ball Grid Array

Solder interconnect failure is a known life limiting failure mechanism that is induced by cyclic temperature excursions. Thermal fatigue reliability of solder interconnects is conventionally assessed by simple temperature cycling test, which applies a constant temperature range, fixed dwell times and ramp rates during the test. However, due to the user controlled power cycles, non-constant workloads, and changes in the surrounding environment, electronics in the field often experience a complex combination of temperature and power cycling. In this study, the effect of power cycling superposed on a simple temperature cycling is experimentally examined. Furthermore, a scheme for modeling the solder interconnect fatigue life of Plastic Ball Grid Array (PBGA) parts under the concurrent power and temperature cycling. Damage, defined as the number of applied cycles over the number of survivable cycles, from the simple temperature cycle and the power cycle are linearly added using Miner's rule, and compared with the concurrent temperature and power cycling test. Cycles to failure of each condition is derived by life testing conducted on Plastic Ball Grid Array (PBGA) assembled with eutectic and SAC305 solder.

Sign in / Sign up

Export Citation Format

Share Document