Temperature Performance of Doping-Free Top-Gate CNT Field-Effect Transistors: Potential for Low- and High-Temperature Electronics

2011 ◽  
Vol 21 (10) ◽  
pp. 1843-1849 ◽  
Author(s):  
Tian Pei ◽  
Zhiyong Zhang ◽  
Zhenxing Wang ◽  
Li Ding ◽  
Sheng Wang ◽  
...  
1995 ◽  
Vol 410 ◽  
Author(s):  
H. Aydin ◽  
M. W. Dryfuse ◽  
M. Tabib-Azar

ABSTRACTFast and slow interface traps can considerably deteriorate the performance of field effect transistors. Slow interface traps, by slowly changing their charge occupancy, contribute to a drift in the quiescent operation point of the transistor, while fast traps deteriorate the device performance by contributing to both amplitude and phase current noise. They also result in a non-equilibrium surface depletion layer between gate and source which increases the gate-to-source parasitic resistance and deteriorates the device transconductance. We examine these different effects and present some preliminary data regarding interface traps in boron-doped 611-SiC.


2016 ◽  
Vol 18 (23) ◽  
pp. 15760-15764 ◽  
Author(s):  
Janghyuk Kim ◽  
Sooyeoun Oh ◽  
Michael A. Mastro ◽  
Jihyun Kim

Exfoliated β-Ga2O3 nano-belt field-effect transistors for air-stable high power and high temperature electronics have been demonstrated.


2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.


1989 ◽  
Vol 25 (12) ◽  
pp. 777 ◽  
Author(s):  
J. Kolodzey ◽  
J. Laskar ◽  
S. Boor ◽  
S. Reis ◽  
A. Ketterson ◽  
...  

2011 ◽  
Vol 50 (1S1) ◽  
pp. 01AD03 ◽  
Author(s):  
Takayuki Sugiyama ◽  
Hiroshi Amano ◽  
Daisuke Iida ◽  
Motoaki Iwaya ◽  
Satoshi Kamiyama ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document