Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Published By IEEE Comput. Soc

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Design of switching blocks tolerating defects/faults in FPGA interconnection resources

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887151 ◽

2002 ◽

Cited By ~ 5

Author(s):

A. Doumar ◽

H. Ito

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A reconfigurable WSI massively data-parallel processing device for cost-effective 3D sensor data processing

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887146 ◽

2002 ◽

Author(s):

R.M. Lea ◽

P.T. Tetnowski ◽

M. Covic

Keyword(s):

Parallel Processing ◽

Data Processing ◽

Cost Effective ◽

Sensor Data ◽

Data Parallel ◽

Processing Device

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A self-correcting active pixel camera

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.886974 ◽

2002 ◽

Cited By ~ 17

Author(s):

I. Koren ◽

G. Chapman ◽

Z. Koren

Keyword(s):

Active Pixel

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Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887158 ◽

2002 ◽

Cited By ~ 2

Author(s):

Y. Katayama ◽

Y. Negishi ◽

S. Morioka

Keyword(s):

Error Correction ◽

Data Retention ◽

Error Correction Code

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Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887148 ◽

2002 ◽

Cited By ~ 9

Author(s):

K. Herrmann ◽

S. Moch ◽

J. Hilgenstock ◽

P. Pirsch

Keyword(s):

Integrated Circuit ◽

Multiprocessor System ◽

Large Area

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Testing the configurability of dynamic FPGAs

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887171 ◽

2002 ◽

Cited By ~ 1

Author(s):

N. Park ◽

S.J. Ruiwale ◽

F. Lombardi

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Self-configuration of a large area integrated multiprocessor system for video applications

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887145 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Rudack ◽

M. Redeker ◽

D. Treytnar ◽

O. Mende ◽

K. Herrmann

Keyword(s):

Multiprocessor System ◽

Large Area

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Path delay fault testability analysis

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887174 ◽

2002 ◽

Cited By ~ 1

Author(s):

J. Sosnowski ◽

T. Wabia ◽

T. Bech

Keyword(s):

Path Delay ◽

Delay Fault ◽

Testability Analysis ◽

Path Delay Fault

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Synthesis of on-line testing control units: flow graph coding/monitoring approach

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887166 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.N. Demidenko ◽

E.M. Levine ◽

V. Piuri

Keyword(s):

Flow Graph ◽

Control Units ◽

On Line

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Design of a fault tolerant multistage interconnection network with parallel duplicated switches

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2000.887152 ◽

2002 ◽

Cited By ~ 5

Author(s):

N. Kamiura ◽

T. Kodera ◽

N. Matsui

Keyword(s):

Fault Tolerant ◽

Interconnection Network ◽

Multistage Interconnection Network

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Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Design of switching blocks tolerating defects/faults in FPGA interconnection resources

A reconfigurable WSI massively data-parallel processing device for cost-effective 3D sensor data processing

A self-correcting active pixel camera

Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs

Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

Testing the configurability of dynamic FPGAs

Self-configuration of a large area integrated multiprocessor system for video applications

Path delay fault testability analysis

Synthesis of on-line testing control units: flow graph coding/monitoring approach

Design of a fault tolerant multistage interconnection network with parallel duplicated switches

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Latest Publications