Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

2002 ◽  
Author(s):  
K. Herrmann ◽  
S. Moch ◽  
J. Hilgenstock ◽  
P. Pirsch
Keyword(s):  
Integrated Circuit ◽  
Multiprocessor System ◽  
Large Area

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

scholarly journals SISTEM PEMESANAN MAKANAN MENGGUNAKAN MIKROKONTROLER ATMEGA8535

Telematika ◽  
2015 ◽  
Vol 7 (1) ◽  
Author(s):  
Wilis Kaswidjanti ◽  
Dessyanto Boedi Prasetyo ◽  
Alamsyah Alamsyah
Keyword(s):  
Integrated Circuit ◽  
Computer Software ◽  
Active Components ◽  
Large Area ◽  
C Language ◽  
Development Tool ◽  
Dinner Table ◽  
Reservation System ◽  
Avr Microcontroller ◽  
Visual Basic 6.0

Some restaurants are to develop the concept by placing the gazebo-gazebo that were located far apart. With a large area and a place to eat with the amount that more and more the restaurant must provide the waitresses in considerable amounts. Often when the waiter is still busy serving the other guests, then there will be visitors restaurants that can not be served well. In addition, the number of waiters that too many would economically burden the employers because it would result in expenditure will be even greater. Then it can be developed an information system involving hardware and software to apply the reservation system that can be done from the tables or places to eat at a restaurant. Systems built using hardware and software. The hardware is built by using the AVR microcontroller device comprising an IC (Integrated Circuit) which is supported by the power supply, as well as some passive and active components. Software on a microcontroller using C language development tool using CodeVision of AVR. While the computer software using Visual Basic 6.0 programming language. Food ordering system that created it can improve services for consumers in terms of booking. Buyers can make a reservation at the dinner table without going through the waitress who had approached the table and write whatever menu you want to order. Additional bookings can also be done through the table without leaving the place or the waiter.

scholarly journals Multiple Use SiPM Integrated Circuit (MUSIC) for Large Area and High Performance Sensors

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 961
Author(s):  
Sergio Gómez ◽  
David Sánchez ◽  
Joan Mauricio ◽  
Eduardo Picatoste ◽  
Andreu Sanuy ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Dynamic Range ◽  
Single Photon ◽  
Experimental Tests ◽  
Output Pulse ◽  
Multiple Use ◽  
Large Area ◽  
The Individual ◽  
Output Driver

The 8-channel Multiple Use Silicon Photo-multiplier (SiPM) Integrated Circuit (MUSIC) Application specific integrated circuit (ASIC) for SiPM anode readout has been designed for applications where large photo-detection areas are required. MUSIC offers three main features: (1) Sum of the eight input channels using a differential output driver, (2) eight individual single ended (SE) analog outputs, and (3) eight individual SE binary outputs using a time over threshold technique. Each functionality, summation and individual readout includes a selectable dual-gain configuration. Moreover, the signal sum implements a dual-gain output providing a 15-bit dynamic range. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with most of the available SiPM devices in the market. Experimental tests show how MUSIC can linearly sum signals from different SiPMs and distinguish even a few photons. Additionally, it provides a single photon output pulse width at half maximum (FWHM) between 5–10 ns for the analog output and a single-photon time resolution (SPTR) around 118 ps sigma using a Hamamatsu SiPM S13360-3075CS for the binary output. Lastly, the summation mode has a power consumption of ≈200 mW, whereas the individual readout consumes ≈30 mW/ch.

Effects of Silicon Wafer Bump Pad Structures on Solder and Cu Pillar Flip-Chip Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000100-000105
Author(s):  
Shirley Asoy ◽  
Scott Exon ◽  
Liping Zhu ◽  
Peter Moon ◽  
Michael Carroll ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Flip Chip ◽  
Failure Modes ◽  
Metal Layer ◽  
Production Environment ◽  
Large Area ◽  
Cu Pillar ◽  
Lack Of Information ◽  
Cu Pillar Bump ◽  
Volume Production

Abstract Solder and Cu pillar flip-chip silicon die technologies have been widely used in chip to package mobile module products. During the early design phase, integrated circuit (IC) designers usually apply standard bump design rules, due to lack of information on the reliability of the metal layer stack-up with different bumping processes. However, module reliability data has demonstrated that the stack-up and thickness of the metal layers in a silicon die has a great effect on package stresses, especially for large area Cu pillar flip chip die. In this paper, the effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly in-line data was collected and analyzed, and is presented in this paper. Reliability testing and failure analysis were performed to verify the failure modes. Guidelines for designing solder and Cu Pillar Flip-chip bump pad structures have been developed, and are presented in this paper.

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