2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.6 ◽

2006 ◽

Cited By ~ 7

Author(s):

Yu-jen Huang ◽

Da-ming Chang ◽

Jin-fu Li

Keyword(s):

Redundancy Analysis ◽

Analysis Scheme

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Testing Reversible 1D Arrays for Molecular QCA

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.63 ◽

2006 ◽

Cited By ~ 10

Author(s):

X. Ma ◽

J. Huang ◽

C. Metra ◽

F. Lombardi

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Error Tolerance of DNA Self-Assembly by Monomer Concentration Control

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.29 ◽

2006 ◽

Cited By ~ 6

Author(s):

Byunghyun Jang ◽

Yong-bin Kim ◽

Fabrizio Lombardi

Keyword(s):

Self Assembly ◽

Monomer Concentration ◽

Error Tolerance

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A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.7 ◽

2006 ◽

Cited By ~ 7

Author(s):

Sandeep Dechu ◽

Manoj Goparaju ◽

Spyros Tragoudas

Keyword(s):

Logic Gates ◽

Threshold Logic ◽

Manufacturing Defects

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Combined software and hardware techniques for the design of reliable IP processors

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.18 ◽

2006 ◽

Cited By ~ 5

Author(s):

M. Rebaudengo ◽

L. Sterpone ◽

M. Violante ◽

C. Bolchini ◽

A. Miele ◽

...

Keyword(s):

Software And Hardware

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Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.58 ◽

2006 ◽

Cited By ~ 5

Author(s):

Ondrej Novak ◽

Zdenek Pliva ◽

Jiri Jenicek ◽

Zbynek Mader ◽

Michal Jarkovsky

Keyword(s):

Self Testing ◽

Hardware Overhead

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Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.50 ◽

2006 ◽

Cited By ~ 14

Author(s):

Mehran Kermani ◽

Arash Reyhani-Masoleh

Keyword(s):

Fault Detection ◽

Advanced Encryption Standard

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Gate Failures Effectively Shape Multiplexing

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.33 ◽

2006 ◽

Cited By ~ 13

Author(s):

V. Beiu ◽

W. Ibrahim ◽

Y.A. Alkhawwar ◽

M.H. Sulieman

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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Cover

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.2 ◽

2006 ◽

Keyword(s):

Fault Tolerance ◽

International Symposium ◽

Ieee International Symposium

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Selecting High-Quality Delay Tests for Manufacturing Test and Debug

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.57 ◽

2006 ◽

Cited By ~ 12

Author(s):

Hangkyu Lee ◽

Suriyaprakash Natarajan ◽

Srinivas Patil ◽

Irith Pomeranz

Keyword(s):

High Quality ◽

Manufacturing Test ◽

Delay Tests

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2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy

Testing Reversible 1D Arrays for Molecular QCA

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

Combined software and hardware techniques for the design of reliable IP processors

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

Gate Failures Effectively Shape Multiplexing

21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Cover

Selecting High-Quality Delay Tests for Manufacturing Test and Debug

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Latest Publications