2019 29th International Conference on Field Programmable Logic and Applications (FPL)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00035 ◽

2019 ◽

Author(s):

Shengwen Liang ◽

Ying Wang ◽

Cheng Liu ◽

Huawei Li ◽

Xiaowei Li

Keyword(s):

Deep Learning ◽

Data Processing

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The CEDARtools Platform – Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00079 ◽

2019 ◽

Author(s):

Thomas Preusser ◽

Alexander Weiss

Keyword(s):

Random Access ◽

External Memory ◽

Low Latency ◽

High Bandwidth ◽

Access Patterns

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Author Index

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00082 ◽

2019 ◽

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Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00069 ◽

2019 ◽

Cited By ~ 2

Author(s):

Hosein Mohammadi Makrani ◽

Farnoud Farahmand ◽

Hossein Sayadi ◽

Sara Bondi ◽

Sai Manoj Pudukotai Dinakarrao ◽

...

Keyword(s):

Machine Learning ◽

High Level Synthesis ◽

Optimal Timing ◽

Resource Usage ◽

Learning Framework ◽

Synthesis Design ◽

High Level

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Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00013 ◽

2019 ◽

Cited By ~ 1

Author(s):

Mark Wijtvliet ◽

Jos Huisken ◽

Luc Waeijen ◽

Henk Corporaal

Keyword(s):

Energy Efficiency ◽

Coarse Grained ◽

Reconfigurable Architectures

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OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00065 ◽

2019 ◽

Cited By ~ 4

Author(s):

Xifan Tang ◽

Edouard Giacomin ◽

Aurelien Alacchi ◽

Baudouin Chauviere ◽

Pierre-Emmanuel Gaillardon

Keyword(s):

Rapid Prototyping

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[Title page iii]

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00002 ◽

2019 ◽

Keyword(s):

Title Page

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Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00042 ◽

2019 ◽

Cited By ~ 3

Author(s):

Farnoud Farahmand ◽

Duc Tri Nguyen ◽

Viet B. Dang ◽

Ahmed Ferozpuri ◽

Kris Gaj

Keyword(s):

Quantum Cryptography ◽

Register Transfer Level ◽

High Level Synthesis ◽

Design Methodologies ◽

Register Transfer ◽

Level Design ◽

Post Quantum Cryptography ◽

High Level ◽

Register Transfer Level Design

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FPGA-Based Simulated Bifurcation Machine

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00019 ◽

2019 ◽

Cited By ~ 3

Author(s):

Kosuke Tatsumura ◽

Alexander R. Dixon ◽

Hayato Goto

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[Copyright notice]

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00003 ◽

2019 ◽

Keyword(s):

Copyright Notice

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2019 29th International Conference on Field Programmable Logic and Applications (FPL)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing

The CEDARtools Platform – Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns

Author Index

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs

[Title page iii]

Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies

FPGA-Based Simulated Bifurcation Machine

[Copyright notice]

Export Citation Format

2019 29th International Conference on Field Programmable Logic and Applications (FPL)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing

The CEDARtools Platform – Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns

Author Index

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs

[Title page iii]

Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies

FPGA-Based Simulated Bifurcation Machine

[Copyright notice]

2019 29th International Conference on Field Programmable Logic and Applications (FPL)
Latest Publications