Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies

2019 ◽  
Author(s):  
Farnoud Farahmand ◽  
Duc Tri Nguyen ◽  
Viet B. Dang ◽  
Ahmed Ferozpuri ◽  
Kris Gaj
Keyword(s):  
Quantum Cryptography ◽  
Register Transfer Level ◽  
High Level Synthesis ◽  
Design Methodologies ◽  
Register Transfer ◽  
Level Design ◽  
Post Quantum Cryptography ◽  
High Level ◽  
Register Transfer Level Design

scholarly journals Register-Transfer Synthesis of Pipelined Data Paths

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 17-32 ◽  
Author(s):  
Nohbyung Park ◽  
Fadi J. Kurdahi
Keyword(s):  
Register Transfer Level ◽  
Design Parameters ◽  
New Approach ◽  
Fixed Set ◽  
Register Transfer ◽  
Clique Partitioning Problem ◽  
Partitioning Problem ◽  
Level Design ◽  
High Level ◽  
Register Transfer Level Design

We present a new approach to the problem of register-transfer level design optimization of pipelined data paths. The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps, and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operations to specific operators, values to registers, and finish the interconnections. We first perform module assignment with the goal of minimizing the interconnect requirements between RT-level components as a preprocessing procedure to the RT-level design. This will result in a smaller netlist which makes the design more compact and the design process more efficient. In addition to reducing the total number of interconnects, this approach will also reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs of shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using this procedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size pipelined designs. This efficient approach will enable designers to explore a larger portion of the design space and trade off various design parameters effectively.

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