2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
Latest Publications

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9781479937899

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Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.25 ◽

2014 ◽

Cited By ~ 3

Author(s):

Arash Saifhashemi ◽

Dylan Hand ◽

Peter A. Beerel ◽

William Koven ◽

Hong Wang

Keyword(s):

Area Optimization

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Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.15 ◽

2014 ◽

Cited By ~ 12

Author(s):

Matheus Moreira ◽

Augusto Neutzling ◽

Mayler Martins ◽

Andre Reis ◽

Renato Ribas ◽

...

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A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.20 ◽

2014 ◽

Cited By ~ 4

Author(s):

Matheus Trevisan Moreira ◽

Michel Evandro Arendt ◽

Ricardo Aquino Guazzelli ◽

Ney Laert Vilar Calazans

Keyword(s):

Low Voltage ◽

Logic Gates ◽

Null Convention Logic

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2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.4 ◽

2014 ◽

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Committees

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.6 ◽

2014 ◽

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An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.10 ◽

2014 ◽

Cited By ~ 2

Author(s):

Guangda Zhang ◽

Wei Song ◽

Jim Garside ◽

Javier Navaridas ◽

Zhiying Wang

Keyword(s):

Network On Chip ◽

Permanent Faults ◽

On Chip

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Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.23 ◽

2014 ◽

Cited By ~ 1

Author(s):

Gang Wang ◽

Xu Wang ◽

Xinke Chen ◽

Shuangbai Xue

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Keynote Talks

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.8 ◽

2014 ◽

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Author index

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.26 ◽

2014 ◽

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Low Power Asynchronous VLSI with NEM Relays

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2014.19 ◽

2014 ◽

Cited By ~ 3

Author(s):

Benjamin Z. Tang ◽

Sunil A. Bhave ◽

Rajit Manohar

Keyword(s):

Low Power ◽

Asynchronous Vlsi

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2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

Table of contents

Committees

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

Keynote Talks

Author index

Low Power Asynchronous VLSI with NEM Relays

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2014 20th IEEE International Symposium on Asynchronous Circuits and SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

Table of contents

Committees

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

Keynote Talks

Author index

Low Power Asynchronous VLSI with NEM Relays

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
Latest Publications