Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis

2014 ◽  
Author(s):  
Arash Saifhashemi ◽  
Dylan Hand ◽  
Peter A. Beerel ◽  
William Koven ◽  
Hong Wang
Keyword(s):  
Area Optimization

scholarly journals Feature-Area Optimization: A Novel SAR Image Registration Method

2016 ◽  
Vol 13 (2) ◽  
pp. 242-246 ◽  
Author(s):  
Fuqiang Liu ◽  
Fukun Bi ◽  
Liang Chen ◽  
Hao Shi ◽  
Wei Liu
Keyword(s):  
Image Registration ◽  
Sar Image ◽  
Registration Method ◽  
Area Optimization

scholarly journals Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller

2019 ◽  
Vol 9 (1) ◽  
pp. 4763-4768
Keyword(s):  
Embedded System ◽  
Optimization Techniques ◽  
Consumer Electronics ◽  
Full Potential ◽  
Disruptive Technologies ◽  
Serial Peripheral Interface ◽  
Area Optimization ◽  
The Embedded System ◽  
On Chip ◽  
Design And Testing

The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half.

scholarly journals Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

2018 ◽  
Vol 11 (1) ◽  
pp. 28-34 ◽  
Author(s):  
Chuandong Chen ◽  
◽  
Bing Lin ◽  
Michelle Zhu ◽  
◽  
...  
Keyword(s):  
Logic Circuits ◽  
Verification Method ◽  
Mixed Polarity ◽  
Area Optimization

Area optimization of comparator layout design by using Cadence Virtuoso tools in 45 nanometer process technology

2021 ◽  
Author(s):  
Michelle Ang Syn Yi ◽  
Razaidi Hussin ◽  
Norhawati Ahmad ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Layout Design ◽  
Process Technology ◽  
Area Optimization
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