Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)
Latest Publications

TOTAL DOCUMENTS

125

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Published By Int. Test Conference

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Test point insertion for compact test sets

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894217 ◽

2002 ◽

Cited By ~ 28

Author(s):

M.J. Geuzebroek ◽

J.T. van der Linden ◽

A.J. van de Goor

Keyword(s):

Test Point ◽

Test Point Insertion ◽

Test Sets ◽

Compact Test

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Using on-chip test pattern compression for full scan SoC designs

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894258 ◽

2002 ◽

Cited By ~ 5

Author(s):

H. Lang ◽

J. Pfeiffer ◽

J. Maguire

Keyword(s):

Test Pattern ◽

Full Scan ◽

On Chip

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Identification of crosstalk switch failures in domino CMOS circuits

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894243 ◽

2002 ◽

Cited By ~ 15

Author(s):

R. Kundu ◽

R.D. Blanton

Keyword(s):

Cmos Circuits

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Adapting scan architectures for low power operation

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894297 ◽

2002 ◽

Cited By ~ 179

Author(s):

L. Whetsel

Keyword(s):

Low Power ◽

Power Operation

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Deception by design: fooling ourselves with gate-level models

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894303 ◽

2002 ◽

Cited By ~ 3

Author(s):

J. Rearick ◽

P. Maxwell

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BISTing data paths at behavioral level

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894262 ◽

2002 ◽

Cited By ~ 2

Author(s):

D. Berthelot ◽

M.-L. Flottes ◽

B. Ronzeyre

Keyword(s):

Behavioral Level

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Bridging the gap between embedded test and ATE

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894191 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Bell ◽

G. Danialy ◽

M. Howells ◽

S. Pateras

Keyword(s):

Embedded Test

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Optimizing the flattened test-generation model for very large designs

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894263 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Wohl ◽

J. Waicukauski

Keyword(s):

Test Generation ◽

Generation Model

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Measuring code edges of ADCs using interpolation and its application to offset and gain error testing

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894224 ◽

2002 ◽

Cited By ~ 5

Author(s):

P.N. Variyam ◽

V. Agrawal

Keyword(s):

Gain Error ◽

Error Testing

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Successful implementation of structured testing

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894223 ◽

2002 ◽

Cited By ~ 9

Author(s):

R.A. Richmond

Keyword(s):

Successful Implementation

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Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Int. Test Conference

Test point insertion for compact test sets

Using on-chip test pattern compression for full scan SoC designs

Identification of crosstalk switch failures in domino CMOS circuits

Adapting scan architectures for low power operation

Deception by design: fooling ourselves with gate-level models

BISTing data paths at behavioral level

Bridging the gap between embedded test and ATE

Optimizing the flattened test-generation model for very large designs

Measuring code edges of ADCs using interpolation and its application to offset and gain error testing

Successful implementation of structured testing

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)
Latest Publications