40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769530478, 9780769530475, 9781424415113

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A Framework for Providing Quality of Service in Chip Multi-Processors

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408267 ◽

2007 ◽

Cited By ~ 3

Author(s):

Fei Guo ◽

Yan Solihin ◽

Li Zhao ◽

Ravishankar Iyer

Keyword(s):

Quality Of Service

Download Full-text

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408252 ◽

2007 ◽

Cited By ~ 1

Author(s):

Onur Mutlu ◽

Thomas Moscibroda

Keyword(s):

Chip Multiprocessors ◽

Memory Access

Download Full-text

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408269 ◽

2007 ◽

Cited By ~ 3

Author(s):

Michael Chu ◽

Rajiv Ravindran ◽

Scott Mahlke

Keyword(s):

Data Access ◽

Multicore Architectures ◽

Fine Grain

Download Full-text

Revisiting the Sequential Programming Model for Multi-Core

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408246 ◽

2007 ◽

Cited By ~ 1

Author(s):

Matthew Bridges ◽

Neil Vachharajani ◽

Yun Zhang ◽

Thomas Jablin ◽

David August

Keyword(s):

Programming Model ◽

Sequential Programming

Download Full-text

Penelope: The NBTI-Aware Processor

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408247 ◽

2007 ◽

Cited By ~ 6

Author(s):

Jaume Abella ◽

Xavier Vera ◽

Antonio Gonzalez

Download Full-text

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408271 ◽

2007 ◽

Cited By ~ 1

Author(s):

Thomas Yeh ◽

Petros Faloutsos ◽

Milos Ercegovac ◽

Sanjay Patel ◽

Glenn Reinman

Keyword(s):

Area Efficient

Download Full-text

40th Annual IEEE/ACM International Symposium on Microarchitecture - Cover

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.46 ◽

2007 ◽

Keyword(s):

International Symposium

Download Full-text

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.33 ◽

2007 ◽

Cited By ~ 258

Author(s):

N. Muralimanohar ◽

R. Balasubramonian ◽

N. Jouppi

Download Full-text

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408265 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jason Zebchuk ◽

Elham Safi ◽

Andreas Moshovos

Keyword(s):

Memory Hierarchy ◽

Coarse Grain ◽

On Chip

Download Full-text

Flattened Butterfly Topology for On-Chip Networks

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) ◽

10.1109/micro.2007.4408254 ◽

2007 ◽

Author(s):

John Kim ◽

James Balfour ◽

William Dally

Keyword(s):

On Chip

Download Full-text

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Framework for Providing Quality of Service in Chip Multi-Processors

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

Revisiting the Sequential Programming Model for Multi-Core

Penelope: The NBTI-Aware Processor

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

40th Annual IEEE/ACM International Symposium on Microarchitecture - Cover

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Flattened Butterfly Topology for On-Chip Networks

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Latest Publications