scholarly journals A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

2007 ◽  
Author(s):  
Jason Zebchuk ◽  
Elham Safi ◽  
Andreas Moshovos
Keyword(s):  
Memory Hierarchy ◽  
Coarse Grain ◽  
On Chip

Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick

2020 ◽  
Author(s):  
Isak Edo Vivancos ◽  
Sayeh Sharify ◽  
Milos Nikolic ◽  
Ciaran Bannon ◽  
Mostafa Mahmoud ◽  
...  
Keyword(s):  
Deep Learning ◽  
Memory Hierarchy ◽  
On Chip

scholarly journals PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy

2021 ◽  
pp. 599-615
Author(s):  
Vladimir Dimić ◽  
Miquel Moretó ◽  
Marc Casas ◽  
Mateo Valero
Keyword(s):  
Memory Hierarchy ◽  
On Chip

Comparative Analysis of Spintronic Memories for Low Power on-chip Caches

SPIN ◽  
2020 ◽  
Vol 10 (04) ◽  
pp. 2050027
Author(s):  
Inderjit Singh ◽  
Balwinder Raj ◽  
Mamta Khosla ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Memory Hierarchy ◽  
System Level ◽  
Computer Memory ◽  
High Frequencies ◽  
Low Leakage ◽  
Research Goal ◽  
On Chip ◽  
Beyond Cmos ◽  
Cache Design ◽  
Level Performance

The continuous downscaling in CMOS devices has increased leakage power and limited the performance to a few GHz. The research goal has diverted from operating at high frequencies to deliver higher performance in essence with lower power. CMOS based on-chip memories consumes significant fraction of power in modern processors. This paper aims to explore the suitability of beyond CMOS, emerging magnetic memories for the use in memory hierarchy, attributing to their remarkable features like nonvolatility, high-density, ultra-low leakage and scalability. NVSim, a circuit-level tool, is used to explore different design layouts and memory organizations and then estimate the energy, area and latency performance numbers. A detailed system-level performance analysis of STT-MRAM and SOT-MRAM technologies and comparison with 22[Formula: see text]nm SRAM technology are presented. Analysis infers that in comparison to the existing 22[Formula: see text]nm SRAM technology, SOT-MRAM is more efficient in area for memory size [Formula: see text][Formula: see text]KB, speed and energy consumption for cache size [Formula: see text][Formula: see text]KB. A typical 256[Formula: see text]KB SOT-MRAM cache design is 27.74% area efficient, 2.97 times faster and consumes 76.05% lesser leakage than SRAM counterpart and these numbers improve for larger cache sizes. The article deduces that SOT-MRAM technology has a promising potential to replace SRAM in lower levels of computer memory hierarchy.

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