The Impact of the Gate Oxide Thickness Reduction on the Gate Induced Floating Body Effect in SOI nMOSFETs

2019 ◽  
Vol 9 (1) ◽  
pp. 305-311
Author(s):  
Paula G. Der Agopian ◽  
Joao A. Martino ◽  
E. Simoen ◽  
C. Claeys
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Thickness Reduction ◽  
Floating Body ◽  
Body Effect ◽  
Floating Body Effect ◽  
Gate Oxide Thickness ◽  
The Impact

scholarly journals Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology

2008 ◽  
Vol 3 (2) ◽  
pp. 91-95
Author(s):  
Paula G. D. Agopian ◽  
João Antonio Martino ◽  
Eddy Simoen ◽  
Cor Claeys
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Electrical Measurements ◽  
Body Effect ◽  
Soi Mosfet ◽  
Floating Body Effect ◽  
Gate Oxide Thickness ◽  
Soi Technology

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.

In-Line Monitor Introduction to Prevent Metallic Contamination in Wet Bench

2005 ◽  
Vol 108-109 ◽  
pp. 637-642 ◽  
Author(s):  
Domenico Mello ◽  
Francesco Cordiano ◽  
Andrea Gerosa ◽  
Margherita Padalino ◽  
Carmelo Gagliano ◽  
...  
Keyword(s):  
Flash Memory ◽  
Production Line ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Contamination Level ◽  
Process Flow ◽  
Gate Oxide Thickness ◽  
Metallic Contaminants ◽  
The Impact ◽  
Metallic Contamination

Contamination controls are very important issues in microelectronics. Any wrong substance introduction in process chambers can cause damages to the production line. Therefore, an extensive control is important because every operation in the process flow (also the most insignificant) can become fatal for the correct functioning of a microelectronic device. The aim of this work is to evaluate the impact of small metallic contamination in the range of 1011÷1012 at/cm2 on silicon substrates implanted with different ion species (As, B and P). An important example of failure related to metallic contamination in a wet bench is reported in this work. The problem appears in a particular class of flash memory devices processing. The electrical parametric test shows a wrong gate oxide thickness and Qbd values out of range, confirmed by early breakdown events and anomalous C-V characteristics. The cause of the failure is morphologically identified off-line by using TEM: the cross section shows a wrong gate oxide thickness and an anomalous interface between gate oxide and silicon substrate. It appears clear that the root failure cause is related to the ion implantation (As in this case) and to the cleaning before gate oxide growth. A short process flow was performed and analyzed step by step in order to identify the failure cause. Many different analytical techniques have been used for each step and all of these provide consistent results. In particular TXRF analysis on wafers processed immediately after cleaning do not show any contamination while Cu and Fe contaminants are observed after sample oxidation and As implant. Metallic contaminants are captured by the substrate after it is implanted with As, and the following RCA cleaning is not able to remove them. In addition, the presence of these metallic contaminants induces roughness of the Si surface and the growth of gate oxide is not controlled (faster oxidation). If different substrates are used, e.g. silicon implanted with B or un-implanted, this contamination level is not detected and does not lead to oxide reliability problems. Once the mechanism of metal contaminant interaction with dopant is identified the introduction of an in-line monitoring is possible, thus allowing to prevent the device failure. The short process loop can be considered as a good method to prepare the substrate before TXRF analysis. After this study the monitor has been integrated in the production line controls

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Short Channel ◽  
Gate Oxide Thickness ◽  
Process Effects ◽  
Dual Gate ◽  
N Dose ◽  
The Impact

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

scholarly journals Roles of Gate-Oxide Thickness Reduction in Scaling Bulk and Thin-Body Tunnel Field-Effect Transistors

2017 ◽  
Vol 55 (3) ◽  
pp. 316 ◽  
Author(s):  
Nguyen Dang Chien ◽  
Dao Thi Kim Anh ◽  
Chun-Hsing Shih
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Swing ◽  
Thickness Reduction ◽  
Thin Body ◽  
Short Channel ◽  
Gate Oxide Thickness

Tunnel field-effect transistor (TFET) has recently been considered as a promising candidate for low-power integrated circuits. In this paper, we present an adequate examination on the roles of gate-oxide thickness reduction in scaling bulk and thin-body TFETs. It is shown that the short-channel performance of TFETs has to be characterized by both the off-current and the subthreshold swing because their physical origins are completely different. The reduction of gate-oxide thickness plays an important role in maintaining low subthreshold swing whereas it shows a less role in suppressing off-state leakage in short-channel TFETs with bulk and thin-body structures. When scaling the gate-oxide thickness, the short-channel effect is suppressed more effectively in thin-body TFETs than in bulk devices. Clearly understanding the roles of scaling gate-oxide thickness is necessary in designing advanced scaled TFET devices.

scholarly journals Effect of Chirality and Oxide Thikness on the Performance of a Ballistic CNTFET

2018 ◽  
Vol 8 (6) ◽  
pp. 4941
Author(s):  
Asma Laribi ◽  
Ahlam Guen Bouazza
Keyword(s):  
Carbon Nanotube ◽  
Potential Model ◽  
Drain Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Promising Candidate ◽  
Gate Oxide Thickness ◽  
Effect Transistor ◽  
The Impact

<p>Since the discovery of 1D nano-object, they are constantly revealing significant physical properties. In this regard, carbon nanotube (CNT) is considered as a promising candidate for application in future nanoelectronics devices like carbon nanotube field effect transistor (CNTFET). In this work, the impact of chirality and gate oxide thikness on the electrical characteristics of a CNTFET are studied. The chiralities used are (5, 0), (10, 0), (19, 0), (26, 0), and the gate oxide thikness varied from 1 to 5 nm.This work is based on a numerical simulation program based on surface potential model. CNTFET Modeling is useful for semiconductor industries for nano scale devices manufacturing. From our results we have observed that the output current increases with chirality increasing.We have also highlight the importance of the gate oxide thickness on the drain current that increases when gate oxide is thin.</p>

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