Review—(Mn,Co)3O4-Based Spinels for SOFC Interconnect Coating Application

With the reduction of solid oxide fuel cell (SOFC) operating temperature to the range of 600 − 800℃, Cr-containing ferritic alloys have become the preferred interconnect material, which unfortunately are susceptible to continuous scale growth and Cr volatility at the SOFC operating temperatures. The (Mn,Co)3O4 spinel system is widely regarded as the most effective coating for SOFC interconnect protection, due to its high thermal and electrical conductivity, adequate coefficient of thermal expansion, and excellent Cr blocking capability. This article reviews the physical and chemical properties of the (Mn,Co)3O4-based spinels; different types of coating precursors and deposition techniques; and the effects of spinel composition, quality and thickness on the coating performance. It is concluded that the spinel coating composition, quality, and thickness are more critical than the coating process in affecting the overall coating performance.

Bundled SWCNT for Global VLSI Interconnects

Carbon nanotube (CNT) has been declared the most attractive and suitable material for VLSI sub-micron technology. Because of CNT's phenomenal physical, electrical, and mechanical properties, it is more advantageous than copper interconnect material. In this chapter, RLC equivalent model of bundled single-wall CNT (SWCNT) is presented by using driver-interconnect-load (DIL) system with CMOS driver. The crosstalk delay is calculated for two-line bus architecture made of two parallel lines (i.e., upper as aggressor and lower as victim). From the simulation, it has been observed that crosstalk delay increases with increase in interconnect length and transition time, whereas it decreases with increased spacing between the lines (aggressor and victim). However, crosstalk delay decreases as the number of tubes in a bundle increases.

Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review

In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).