scholarly journals Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review

2018 ◽  
Vol 4 (3) ◽  
pp. 49 ◽  
Author(s):  
Arnab Hazra ◽  
Sukumar Basu
Keyword(s):  
Large Scale ◽  
Graphene Nanoribbons ◽  
High Current Density ◽  
Graphene Film ◽  
Side Wall ◽  
Graphene Nanoribbon ◽  
Practical Implementation ◽  
High Electron ◽  
On Chip ◽  
Interconnect Material

In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).

Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects

2020 ◽  
Vol 29 (12) ◽  
pp. 2050185 ◽  
Author(s):  
Himanshu Sharma ◽  
Karmjit Singh Sandha
Keyword(s):  
Integrated Circuit ◽  
Fermi Energy ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Layer Graphene ◽  
Parasitic Parameters ◽  
On Chip ◽  
Power Delay Product ◽  
Technology Nodes ◽  
The Impact

Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

scholarly journals Graphene Nanoribbon Gap Waveguides for Dispersionless and Low-Loss Propagation with Deep-Subwavelength Confinement

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1302
Author(s):  
Zhiyong Wu ◽  
Lei Zhang ◽  
Tingyin Ning ◽  
Hong Su ◽  
Irene Ling Li ◽  
...  
Keyword(s):  
High Performance ◽  
Chemical Potential ◽  
Shape Change ◽  
Optical Switch ◽  
Pulse Amplitude ◽  
Propagation Distance ◽  
Graphene Nanoribbon ◽  
Low Loss ◽  
High Loss ◽  
On Chip

Surface plasmon polaritons (SPPs) have been attracting considerable attention owing to their unique capabilities of manipulating light. However, the intractable dispersion and high loss are two major obstacles for attaining high-performance plasmonic devices. Here, a graphene nanoribbon gap waveguide (GNRGW) is proposed for guiding dispersionless gap SPPs (GSPPs) with deep-subwavelength confinement and low loss. An analytical model is developed to analyze the GSPPs, in which a reflection phase shift is employed to successfully deal with the influence caused by the boundaries of the graphene nanoribbon (GNR). It is demonstrated that a pulse with a 4 μm bandwidth and a 10 nm mode width can propagate in the linear passive system without waveform distortion, which is very robust against the shape change of the GNR. The decrease in the pulse amplitude is only 10% for a propagation distance of 1 μm. Furthermore, an array consisting of several GNRGWs is employed as a multichannel optical switch. When the separation is larger than 40 nm, each channel can be controlled independently by tuning the chemical potential of the corresponding GNR. The proposed GNRGW may raise great interest in studying dispersionless and low-loss nanophotonic devices, with potential applications in the distortionless transmission of nanoscale signals, electro-optic nanocircuits, and high-density on-chip communications.

scholarly journals Stabilized Hydroxide-Mediated Nickel-Based Electrocatalysts for High-Current-Density Hydrogen Evolution in Alkaline Media

2021 ◽  
Author(s):  
Yuting Luo ◽  
Zhiyuan Zhang ◽  
Fengning Yang ◽  
Jiong Li ◽  
Zhibo Liu ◽  
...  
Keyword(s):  
Water Splitting ◽  
Large Scale ◽  
Fossil Fuels ◽  
High Current Density ◽  
Critical Energy ◽  
Alkaline Media ◽  
Scale Production ◽  
High Current ◽  
Large Scale Production ◽  
Electrochemical Water Splitting

Large-scale production of green hydrogen by electrochemical water splitting is considered as a promising technology to address critical energy challenges caused by the extensive use of fossil fuels. Although nonprecious...

scholarly journals Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec
Keyword(s):  
Code Generation ◽  
State Of The Art ◽  
Power Grids ◽  
Practical Implementation ◽  
System A ◽  
Measuring Devices ◽  
Point Representation ◽  
Measurement Algorithm ◽  
On Chip ◽  
Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

scholarly journals Nanolaser-based emulators of spin Hamiltonians

Nanophotonics ◽  
2020 ◽  
Vol 9 (13) ◽  
pp. 4193-4198 ◽  
Author(s):  
Midya Parto ◽  
William E. Hayenga ◽  
Alireza Marandi ◽  
Demetrios N. Christodoulides ◽  
Mercedeh Khajavikhan
Keyword(s):  
Large Scale ◽  
Optimization Problems ◽  
Exchange Interactions ◽  
Np Hard ◽  
Spin Models ◽  
Geometric Frustration ◽  
Spin Hamiltonians ◽  
Hard Problems ◽  
On Chip ◽  
Classical Spin Models

AbstractFinding the solution to a large category of optimization problems, known as the NP-hard class, requires an exponentially increasing solution time using conventional computers. Lately, there has been intense efforts to develop alternative computational methods capable of addressing such tasks. In this regard, spin Hamiltonians, which originally arose in describing exchange interactions in magnetic materials, have recently been pursued as a powerful computational tool. Along these lines, it has been shown that solving NP-hard problems can be effectively mapped into finding the ground state of certain types of classical spin models. Here, we show that arrays of metallic nanolasers provide an ultra-compact, on-chip platform capable of implementing spin models, including the classical Ising and XY Hamiltonians. Various regimes of behavior including ferromagnetic, antiferromagnetic, as well as geometric frustration are observed in these structures. Our work paves the way towards nanoscale spin-emulators that enable efficient modeling of large-scale complex networks.

scholarly journals Simba

2021 ◽  
Vol 64 (6) ◽  
pp. 107-116
Author(s):  
Yakun Sophia Shao ◽  
Jason Cemons ◽  
Rangharajan Venkatesan ◽  
Brian Zimmer ◽  
Matthew Fojtik ◽  
...  
Keyword(s):  
Deep Learning ◽  
Large Scale ◽  
Data Locality ◽  
Coarse Grained ◽  
Batch Size ◽  
Peak Performance ◽  
Large Scale Systems ◽  
High Area ◽  
On Chip ◽  
And Storage

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with finegrained chiplets for deep learning inference, an application domain with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with a batch size of one, delivering an inference latency of 0.50 ms.

scholarly journals Modeling of Thermal Effects in Semiconductor Structures

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 53-58
Author(s):  
Christopher M. Snowden
Keyword(s):  
Thermal Effects ◽  
Large Scale ◽  
High Electron Mobility Transistors ◽  
Thermal Modelling ◽  
High Electron ◽  
Temperature Model ◽  
Active Devices ◽  
Electron Mobility Transistors ◽  
Fully Coupled ◽  
Scale Surface

A fully coupled electro-thermal hydrodynamic model is described which is suitable for modelling active devices. The model is applied to the non-isothermal simulation of pseudomorphic high electron mobility transistors (pHEMTs). A large-scale surface temperature model is described which allows thermal modelling of semiconductor devices and monolithic circuits. An example of the application of thermal modelling to monolithic circuit characterization is given.

B, N-codoped graphene nanoribbons supported Pd nanoparticles for ethanol electrooxidation enhancement

2016 ◽  
Vol 4 (13) ◽  
pp. 4929-4933 ◽  
Author(s):  
Qi Liu ◽  
Jinchen Fan ◽  
Yulin Min ◽  
Tong Wu ◽  
Yan Lin ◽  
...  
Keyword(s):  
Hydrothermal Method ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Pd Nanoparticles ◽  
Ethanol Electrooxidation ◽  
One Pot ◽  
Supported Pd

In this study, B, N-codoped graphene nanoribbons (BN-GNRs) were prepared on a large scale via a one-pot hydrothermal method with GNRs and an ammonium fluoroborate (NH4BF4) mixture and served as the support for Pd loading targeted for efficient ethanol electrooxidation.

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