New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

Single EXCCII-Based Analog Multiplier Structure

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18[Formula: see text][Formula: see text]m technology and post layout simulation results are given to verify the theoretical aspects.