Energy-Efficient Word-Serial Processor for Field Multiplication and Squaring Suitable for Lightweight Authentication Schemes in RFID-Based IoT Applications

Radio-Frequency Identification (RFID) technology is a crucial technology used in many IoT applications such as healthcare, asset tracking, logistics, supply chain management, assembly, manufacturing, and payment systems. Nonetheless, RFID-based IoT applications have many security and privacy issues restricting their use on a large scale. Many authors have proposed lightweight RFID authentication schemes based on Elliptic Curve Cryptography (ECC) with a low-cost implementation to solve these issues. Finite-field multiplication are at the heart of these schemes, and their implementation significantly affects the system’s overall performance. This article presents a formal methodology for developing a word-based serial-in/serial-out semisystolic processor that shares hardware resources for multiplication and squaring operations in GF(2n). The processor concurrently executes both operations and hence reduces the execution time. Furthermore, sharing the hardware resources provides savings in the area and consumed energy. The acquired implementation results for the field size n=409 indicate that the proposed structure achieves a significant reduction in the area–time product and consumed energy over the previously published designs by at least 32.3% and 70%, respectively. The achieved results make the proposed design more suitable to realize cryptographic primitives in resource-constrained RFID devices.

Study on the Application of FPGA in Magnetic Flux Leakage Acquisition System

Embedded CPU in traditional magnetic flux leakage detection system was used as the master controller. CPU is serial processor, which making it difficult to collect the large amounts of real-time data. While FPGA has the advantages of high integration, high speed processing, parallel processing. FPGA is applied to magnetic flux leakage acquisition system to solve data acquisition problem. It comes up with the designs of a multi-channel magnetic flux leakage signal selection control module, A/D conversion module and communication module in VHDL language on QuartusII. The experimental results show that each module of the magnetic flux leakage acquisition system based on FPGA can meet the requirements, and can correctly collect magnetic flux leakage signal, convert and transmit data. Design of FPGA-based is programmable in the field, magnetic flux leakage collection system can be flexibly designed for different occasions, and has independent intellectual property rights.

Canonical relations between intelligence and aggressiveness

Relation between results obtained from 25 tests for estimation of efficiency of perceptual, serial and parallel processor and 8 tests that estimate different modalities of aggressiveness, were analyzed under the biorthogonal model of canonical correlation analysis, on a sample of 647 male subjects, age between 19 to 27. The results show that there is significant, medium high (0,65), logically negative canonical correlation between cognitive efficiency and aggressiveness. Canonical factor derived from cognitive tests was similar to general cognitive factor because all cognitive tests had substantial correlation with it, whereby correlations of tests of serial processing were systematically higher than correlation of tests of parallel and particularly of perceptual processing. Canonic factor derived from tests of aggressiveness was not similar to invert scaled factor of aggressiveness of second order because tests of basic aggressiveness and impulsiveness that were otherwise dominant salient of general factor of aggressiveness, did not have significant correlation with canonical factor derived from tests of aggressiveness. According to that, it seams that inferior functioning of cognitive and particularly serial processor is connected only to those modalities of aggressiveness where there are also disorders of other conative regulators, especially systems for coordination and control of conative functions, but not with basic aggressiveness. That, basically biological characteristic of system for regulation and control of attack reaction, is not, according to all, in significant correlation with efficiency of cognitive processors.

The Syntax of Parallelism

One of the problems associated with the introduction of parallel processors is the so called “dusty deck” problem. A solution entails the development of optimizing compilers that transform programs previously written for a conventional serial processor into functionally equivalent programs that exploit the parallel processing capabilities of the new multiprocessor machines. We introduce a function Composition Model that models parallel architectures as a hierarchy of syntactic function definitions. Position in the hierarchy is equivalent to parallel time complexity in the modelled architecture. Other parallel concepts such as global vs. local communications, concurrency or exclusivity of read and write, and the number of processors used in a computation, are modelled as well. We rigorously prove that a compiler that optimizes a program for parallelism on a CREW PRAM is not effectively computable, even if it is also given an optimal serial program for the same task and a time bounding function. It turns out that the function composition model is similar to some traditional models, such as the Grzegorczyk Hierarchy. Our parallel interpretation of the Grzegorczyk Hierarchy offers new insights and admits a new cleaner and more elegant definition of the hierarchy with a single base class, as opposed to Grzegorczyk’s three.