Microstructure and reliability of hybrid interconnects by Au stud bump with Sn-0.7Cu solder for flip chip power device packaging

2016 ◽  
Vol 66 ◽  
pp. 134-142 ◽  
Author(s):  
Hongjun Ji ◽  
Jiao Wang ◽  
Mingyu Li
Keyword(s):  
Flip Chip ◽  
Power Device ◽  
Au Stud Bump

Electromigration in Power Devices

2020 ◽  
Vol 2020 (1) ◽  
pp. 000078-000084
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Circuit Board ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Optimization of the Au Stud Bump Number for the Flip-Chip Packaged InGaN LEDs

2013 ◽  
Vol 753-755 ◽  
pp. 2515-2520
Author(s):  
Yun Yun Zhang ◽  
Xiao Wei Sun ◽  
Wen Yu Kuo ◽  
Liann Be Chang ◽  
Bohr Ran Huang ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Thermal Imaging ◽  
Flip Chip ◽  
Heat Dissipation ◽  
Optical Performance ◽  
Imaging Analysis ◽  
The Poor ◽  
Au Stud Bump ◽  
Heat Spreading ◽  
Good Heat

Au stud bump can provide a good heat spreading path for the flip-chip LED due to its high thermal conductivity (300 W/mK) . In this paper, we compared four flip-chip LED devices with four different numbers of Au stud bumps. The thermal imaging analysis indicates that the heat dissipation is proportional to the number of Au stud bump. However, when the number of Au stud bumps was larger than 24, the heat dissipation performance will become deteriorated due to the poor bonding between grain and substrate. Therefore, the number of Au stud bumps was optimized to be 20 to 24, which can be employed to develop flip-chip LEDs with optimum electrical and optical performance.

scholarly journals Electromigration in Power Devices: A Combined Effect of Electromigration and Thermal Migration

2021 ◽  
Vol 18 (1) ◽  
pp. 1-6
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Thermal Migration ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction in Alternative Accelerated Mechanical Cycling Test

2019 ◽  
Vol 141 (3) ◽  
Author(s):  
Mahsa Montazeri ◽  
Cody J. Marbut ◽  
David Huitink
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Mechanical Stresses ◽  
Power Device ◽  
Reliability Test ◽  
Test Duration ◽  
Force Frequency ◽  
Solder Interconnects ◽  
Mechanical Cycling ◽  
Power Cycling

In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.

Analysis of Characteristics of Halogen and LED Automobile Lamps

2020 ◽  
pp. 57-62
Author(s):  
Olga Yu. Kovalenko ◽  
Yulia A. Zhuravlyova
Keyword(s):  
Power Consumption ◽  
Flip Chip ◽  
Weather Conditions ◽  
Luminous Flux ◽  
Luminous Efficacy ◽  
Colour Temperature ◽  
Study Results ◽  
Calculation Results ◽  
Mandatory Rules ◽  
Halogen Lamps

This work contains analysis of characteristics of automobile lamps by Philips, KOITO, ETI flip chip LEDs, Osram, General Electric (GE), Gtinthebox, OSLAMPledbulbs with H1, H4, H7, H11 caps: luminous flux, luminous efficacy, correlated colour temperature. Characteristics of the studied samples are analysed before the operation of the lamps. The analysis of the calculation results allows us to make a conclusion that the values of correlated colour temperature of halogen lamps are close to the parameters declared by manufacturers. The analysis of the study results has shown that, based on actual values of correlated colour temperature, it is not advisable to use LED lamps in unfavourable weather conditions (such as rain, fog, snow). The results of the study demonstrate that there is a slight dispersion of actual values of luminous flux of halogen lamps by different manufacturers. Maximum variation between values of luminous flux of different lamps does not exceed 14 %. The analysis of the measurement results has shown that actual values of luminous flux of all halogen lamps comply with the mandatory rules specified in the UN/ECE Regulation No. 37 and luminous flux of LED lamps exceeds maximum allowable value by more than 8 %. Luminous efficacy of LED lamps is higher than that of halogen lamps: more than 82 lm/W and lower power consumption. The results of the measurements have shown that power consumption of a LED automobile lamp is lower than that of similar halogen lamps by 3 times and their luminous efficacy is higher by 5 times.

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