Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

HIGH PERFORMANCE MAC UNIT USING MODIFIED SIGN EXTENSION ALGORITHM AND A NEW HIGH-SPEED ALU IN DSP-CORE

This paper describes a high performance multiply-accumulator (MAC) unit in DSP-core. Since the most critical timing path of the DSP lies in the MAC, great endeavors have been paid to speed it up. The MAC unit can perform fixed-point operation with rounding optional, on operands with a throughput of 1 cycle. In this design, the modified sign extension algorithm is presented to eliminate the sign bits array of partial products to reduce computation time and area. Further increase in speed is achieved by using a new three 40 bit inputs (also known as operands) high-speed arithmetic logical unit (ALU) to shorten the delay of the critical path.