Efficient sign extension for multiple addition

2003 ◽  
Author(s):  
Robert T. Grisamore ◽  
Earl E. Swartzlander, Jr.
Keyword(s):  
Sign Extension ◽  
Multiple Addition

Multiple addition bioassay of Tjeukemeer water

Hydrobiologia ◽  
1982 ◽  
Vol 88 (3) ◽  
pp. 233-244 ◽  
Author(s):  
H. de Haan ◽  
J. B. W. Wanders ◽  
J. R. Moed
Keyword(s):  
Multiple Addition

scholarly journals Chitosan multiple addition enhances laccase production from Trametes versicolor

2015 ◽  
Vol 38 (10) ◽  
pp. 1973-1981 ◽  
Author(s):  
Abiodun Emmanuel Adekunle ◽  
Feng Wang ◽  
Jianhua Hu ◽  
Anzhou Ma ◽  
Chen Guo ◽  
...  
Keyword(s):  
Trametes Versicolor ◽  
Laccase Production ◽  
Multiple Addition

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

Effect Multiple Addition (TiO2 and Fly Ash) on Wear Behavior and Hardness of 2024 Al Alloy

2021 ◽  
Vol 1039 ◽  
pp. 201-208
Author(s):  
Ruaa A. Salman ◽  
Naser K. Zedin
Keyword(s):  
Wear Resistance ◽  
Fly Ash ◽  
Wear Rate ◽  
Wear Behavior ◽  
Weight Percent ◽  
Al Alloy ◽  
Sliding Speed ◽  
Multiple Addition

This research is devoted to study the effect of addition (2%) TiO2 with different weight percent of fly ash particulate (0, 2, 4, 6%) to 2024 Al alloy on the wear behavior and hardness. The alloy was fabricated by the liquid metallurgy method. The results founds that the wear rate decreased from 0.55 with 0% fly ash to 0.18 at addition percentage of 6% fly ash. Also, the results reveal increasing the samples wear rate with increasing the load and loaded time. The rate of wear was decreased with increasing the sliding speed. Also, the values of hardness increased from 120VH to 160VH with rising the fly ash from 0% to 6%. Keywords: Fly Ash addition, TiO2, 2024 Al Alloy, Wear Resistance, Hardness.

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