Evaluation of the Stability on the New Alkaline Copper Bulk Slurry

At present, the chemical mechanical polishing is the only means for global planarization of an integrated circuit. After the node of the integrated circuit processing comes into 45nm, the diameter of wafer is 300mm, and the copper interconnect layer is above the 10 layer. In the same time the new low dielectric constant materials are used to the integrated circuit processing. That requires the property of the slurry used in the chemical mechanical polishing stricter. So the domestic and international companies carry out a series research works. Based on investigation and research for many years, the new alkaline copper rough slurry has been developed by the teachers and students in the Hebei University of Technology. The slurry has advantages as disadvantages. The composition of cost-effective slurry is simple and the effect of chemical mechanical polishing is good. But its stability is poor. In order to improve the stability, the compositions of the slurry need to adjust.The new alkaline copper rough slurry composed by abrasive, surface, chelating agent, oxidizing agent and deionized water. Experiments investigate the influence rule of copper polishing rate by the concentration of abrasive, the content of surface, the content of oxidizing agent and the content of chelating agent. The conclusion is arrived. When the concentration of abrasive is 4%, the content of surfactant is 10ml/l, the content of chelating agent is 10ml/l and the content of oxidizing agent is 5ml/l, the copper polishing rate keep 5000 Å /min.

Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing

Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

Comparison of Conductance and Capacitance techniques for Measurement of Interface States in Thin Oxides

ABSTRACTCurrent trends in integrated circuit processing project gate insulators with oxide equivalent thicknesses of 1.5 to 1.0 nm. Gate oxides in this thickness range have oxide capacitances of 1 to 5 μF/cm2. When oxide capacitances are this large, traditional high-frequency capacitance-voltage techniques for measuring interface states can be inaccurate. We show that a combination of high and low frequency capacitance-voltage data, along with frequency dependent conductance methods, produce more accurate results.