interconnect noise Latest Research Papers

A New Computing Paradigm Leveraging Interconnect Noise for Digital Electronics Under Extreme Environments

2019 IEEE Aerospace Conference ◽

10.1109/aero.2019.8741746 ◽

2019 ◽

Author(s):

Naveen Kumar Macha ◽

Bhavana Tejaswini Repalle ◽

Md Arif Iqbal ◽

Mostafizur Rahman

Keyword(s):

Extreme Environments ◽

Digital Electronics ◽

Computing Paradigm ◽

Interconnect Noise

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Subthreshold Interconnect Noise Analysis

Energy Systems in Electrical Engineering - Compact Models and Performance Investigations for Subthreshold Interconnects ◽

10.1007/978-81-322-2132-6_5 ◽

2014 ◽

pp. 67-82

Author(s):

Rohit Dhiman ◽

Rajeevan Chandel

Keyword(s):

Noise Analysis ◽

Interconnect Noise

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An improved interconnect noise methodology for reduced pessimism using dAP model

2011 IEEE Symposium on Industrial Electronics and Applications ◽

10.1109/isiea.2011.6108717 ◽

2011 ◽

Author(s):

Wong Wai Mun ◽

Arjuna Bin Marzuki ◽

Wong Yew Honn

Keyword(s):

Interconnect Noise

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Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

International Journal of Engineering and Technology ◽

10.7763/ijet.2011.v3.305 ◽

2011 ◽

Vol 3 (6) ◽

pp. 684-688

Author(s):

P. V. Hunagund ◽

A. B. Kalpana

Keyword(s):

Integrated Circuits ◽

High Speed ◽

Optimization Technique ◽

Noise Optimization ◽

Interconnect Noise

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Power dissipation and interconnect noise challenges in nanometer CMOS technologies

IEEE Potentials ◽

10.1109/mpot.2010.935825 ◽

2010 ◽

Vol 29 (3) ◽

pp. 26-31 ◽

Cited By ~ 10

Author(s):

Ndubuisi Ekekwe

Keyword(s):

Power Dissipation ◽

Nanometer Cmos ◽

Interconnect Noise

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Interconnect Noise Analysis and Optimization Techniques

Interconnect Noise Optimization in Nanometer Technologies ◽

10.1007/0-387-29366-3_3 ◽

2006 ◽

pp. 29-43

Keyword(s):

Noise Analysis ◽

Optimization Techniques ◽

Interconnect Noise

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New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks

IEEE Transactions on Advanced Packaging ◽

10.1109/tadvp.2005.862647 ◽

2006 ◽

Vol 29 (1) ◽

pp. 11-20 ◽

Cited By ~ 2

Author(s):

A. Deutsch ◽

H.H. Smith ◽

B.J. Rubin ◽

B.L. Krauter ◽

G.V. Kopcsay

Keyword(s):

Transmission Line ◽

Chip Data ◽

Lossy Transmission ◽

Data Buses ◽

Combined Simulation ◽

On Chip ◽

Lossy Transmission Line ◽

Interconnect Noise

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The effect of power islands on delta-I noise, interconnect noise, and timing for wide, on-chip data-buses

IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005. ◽

10.1109/epep.2005.1563765 ◽

2006 ◽

Author(s):

A. Deutsch ◽

H.H. Smith ◽

H.-M. Huang ◽

A. Elfadel

Keyword(s):

Chip Data ◽

Data Buses ◽

On Chip ◽

Power Islands ◽

Interconnect Noise

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Interconnect Noise Optimization in Nanometer Technologies

10.1007/0-387-29366-3 ◽

2006 ◽

Keyword(s):

Noise Optimization ◽

Interconnect Noise

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Managing Substrate and Interconnect Noise from High Performance Repeater Insertion in a Mixed-Signal Environment

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1464662 ◽

2005 ◽

Author(s):

R.M. Secareanu ◽

S.K. Banerjee ◽

O. Hartin ◽

V. Fernandez ◽

E.G. Friedman

Keyword(s):

High Performance ◽

Mixed Signal ◽

Signal Environment ◽

Interconnect Noise

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interconnect noise
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

A New Computing Paradigm Leveraging Interconnect Noise for Digital Electronics Under Extreme Environments

Subthreshold Interconnect Noise Analysis

An improved interconnect noise methodology for reduced pessimism using dAP model

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Power dissipation and interconnect noise challenges in nanometer CMOS technologies

Interconnect Noise Analysis and Optimization Techniques

New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks

The effect of power islands on delta-I noise, interconnect noise, and timing for wide, on-chip data-buses

Interconnect Noise Optimization in Nanometer Technologies

Managing Substrate and Interconnect Noise from High Performance Repeater Insertion in a Mixed-Signal Environment

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interconnect noiseRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

A New Computing Paradigm Leveraging Interconnect Noise for Digital Electronics Under Extreme Environments

Subthreshold Interconnect Noise Analysis

An improved interconnect noise methodology for reduced pessimism using dAP model

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Power dissipation and interconnect noise challenges in nanometer CMOS technologies

Interconnect Noise Analysis and Optimization Techniques

New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks

The effect of power islands on delta-I noise, interconnect noise, and timing for wide, on-chip data-buses

Interconnect Noise Optimization in Nanometer Technologies

Managing Substrate and Interconnect Noise from High Performance Repeater Insertion in a Mixed-Signal Environment

interconnect noise
Recently Published Documents