Formation of intrinsic and silicon defects in MoO3 under varied oxygen partial pressure and temperature conditions: an ab initio DFT investigation

DFT simulations predict how varied MoO3 preparation conditions could change intrinsic defect concentrations and avoid silicon contamination in photovoltaic applications.

Nonwetting Effects of Si Contamination on Cu Bumps of a Flip Chip Package—A Case Study

Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.