2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Latest Publications

TOTAL DOCUMENTS

933

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781728133201

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Symmetrical Buffered Clock Tree Synthesis Considering NBTI

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180674 ◽

2020 ◽

Author(s):

Deokkeun Oh ◽

Mujun Choi ◽

Juho Kim

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Tree Synthesis

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A Multi-Feature Nonlinear-SVM Seizure Detection Algorithm with Patient-Specific Channel Selection and Feature Customization

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180729 ◽

2020 ◽

Cited By ~ 1

Author(s):

M. Reza Karimi ◽

Hossein Kassiri

Keyword(s):

Seizure Detection ◽

Channel Selection ◽

Detection Algorithm ◽

Patient Specific

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Metaplasticity in Multistate Memristor Synaptic Networks

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180512 ◽

2020 ◽

Author(s):

Fatima Tuz Zohora ◽

Abdullah M. Zyarah ◽

Nicholas Soures ◽

Dhireesha Kudithipudi

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Zebra: Memory Bandwidth Reduction for CNN Accelerators with Zero Block Regularization of Activation Maps

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180865 ◽

2020 ◽

Author(s):

Hsu-Tung Shih ◽

Tian-Sheuan Chang

Keyword(s):

Memory Bandwidth ◽

Bandwidth Reduction

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FedExg: Federated Learning with Model Exchange

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9181029 ◽

2020 ◽

Author(s):

Zhicheng Mao ◽

Wenrui Dai ◽

Chenglin Li ◽

Yuhui Xu ◽

Shanghong Wang ◽

...

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A Self-Compensated, Low-Offset Voltage Buffer for Input Impedance Boosting in Chopped Neural Front-Ends

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180910 ◽

2020 ◽

Author(s):

Stefan Reich ◽

Markus Sporer ◽

Maurits Ortmanns

Keyword(s):

Input Impedance ◽

Offset Voltage ◽

Low Offset

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Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9181068 ◽

2020 ◽

Author(s):

Khalid Al-Hawaj ◽

Olalekan Afuye ◽

Shady Agwa ◽

Alyssa Apsel ◽

Christopher Batten

Keyword(s):

In Situ Processing ◽

Bit Serial

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OTA-Free MASH 2–2 Noise Shaping SAR ADC: System and Design Considerations

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180832 ◽

2020 ◽

Author(s):

Masoume Akbari ◽

Mohammad Honarparvar ◽

Yvon Savaria ◽

Mohamad Sawan

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

Design Considerations

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Unsupervised Multiple Granularities Attention-Attribute Learning for Person Re-Identification

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180731 ◽

2020 ◽

Author(s):

Rui Yang ◽

Song Wu ◽

Guoqiang Xiao

Keyword(s):

Attribute Learning ◽

Multiple Granularities

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A Self-Powered Piezoelectric Energy Harvesting Interface Circuit Based on Adaptive SSHI with Fully Integrated Switch Control

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180969 ◽

2020 ◽

Author(s):

Shaochen Xi ◽

Weimin Li ◽

Jianping Guo ◽

Junrui Liang

Keyword(s):

Energy Harvesting ◽

Piezoelectric Energy Harvesting ◽

Interface Circuit ◽

Fully Integrated ◽

Piezoelectric Energy ◽

Switch Control ◽

Self Powered

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2020 IEEE International Symposium on Circuits and Systems (ISCAS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Symmetrical Buffered Clock Tree Synthesis Considering NBTI

A Multi-Feature Nonlinear-SVM Seizure Detection Algorithm with Patient-Specific Channel Selection and Feature Customization

Metaplasticity in Multistate Memristor Synaptic Networks

Zebra: Memory Bandwidth Reduction for CNN Accelerators with Zero Block Regularization of Activation Maps

FedExg: Federated Learning with Model Exchange

A Self-Compensated, Low-Offset Voltage Buffer for Input Impedance Boosting in Chopped Neural Front-Ends

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

OTA-Free MASH 2–2 Noise Shaping SAR ADC: System and Design Considerations

Unsupervised Multiple Granularities Attention-Attribute Learning for Person Re-Identification

A Self-Powered Piezoelectric Energy Harvesting Interface Circuit Based on Adaptive SSHI with Fully Integrated Switch Control

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Latest Publications