Radiation Hardness of Silicon Carbide upon High-Temperature Electron and Proton Irradiation

The radiation hardness of silicon carbide with respect to electron and proton irradiation and its dependence on the irradiation temperature are analyzed. It is shown that the main mechanism of SiC compensation is the formation of deep acceptor levels. With increasing the irradiation temperature, the probability of the formation of these centers decreases, and they are partly annealed out. As a result, the carrier removal rate in SiC becomes ~6 orders of magnitude lower in the case of irradiation at 500 °C. Once again, this proves that silicon carbide is promising as a material for high-temperature electronics devices.

Photoluminescence Characterization of Fluorescent Sic with High Boron and Nitrogen Concentrations

The dependence of optical properties on impurity concentrations and excitation power was explored. In particular, it was found that the peak shift of photoluminescence (PL) is proportional to the boron concentration. This might be due to donor–acceptor pair (DAP) recombination via double deep acceptor levels (D-centers), where the occupancy of the D*-center increased with the B concentration, and the recombination via the D*-center for longer wavelengths became dominant. Moreover, the relative constants B and C were calculated by BC model fitting from the internal quantum efficiency (IQE) curve as a function of excitation power. The theoretical extrapolation based on BC model predicted that high impurity concentrations are sufficient to suppress the droop phenomenon of efficiency induced by the increased excitation power.

Influence of high-temperature annealing on the characteristics of fast electron-irradiated p-n-structures based on neutron doped silicon

The investigation results of the annealing influence (Тann = 300–800 ºС) on the minority charge currier lifetime tP in the n-base of p-n-structures, manufactured on the base of neutron transmutation doped silicon (NTD) КОФ300, irradiated at room temperature by different fluences (F = 1 · 1014 – 3 · 1016 cm–2) of electrons with the energy of Еe = 4 MeV are presented. It is established that at low electron fluences (F = 1 · 1014 cm–2), the annealing of minority charge currier lifetime tP in the n-base of p-n-structures occurs in two stages: the first – 320–400 ºС and the second – 550–650 ºС. At higher electron fluences (F = 5 · 1015–2 · 1016 cm–2), three annealing stages occur: the first – 400–450 ºС, the second – 520–650 ºС and the third – 710–770 ºС. At this, the structure barrier capacitance C dependences on Тann at high electron fluences show the geometry capacitance up to the annealing temperatures Тann = 400 ºС. In the annealing temperature range of Тann = 420–570 ºС, the increase in С with maximum is seen at Тann = 480 ºС and a subsequent decrease in the geometry capacitance is seen in the annealing temperature range of Тann = 600–670 ºС, and then again the increase in С occurs in the annealing temperature range of Тann = 720–770 ºС reaching the С values corresponding to those of the non-irradiated samples in the annealing temperature range of Тann = 770–800 ºС. The analysis of the DLTS-spectra of the investigated structures has allowed establishing the formation in the annealing process of the deep acceptor level ЕС – 0.68 eV at Тann > 400 ºС, the deep donor level ЕС – 0.32 eV in the annealing temperature range of Тann = 420–570 ºС and the deep acceptor level ЕС – 0.53 eV at Тann > 700 ºС, which satisfactorily explains the dependences of t P and С on Тann obtained in this paper.

A channel-potential-based surface potential model and a turn-on DC channel-potential-based drain current model for fully-depleted poly-Si thin film transistors including tail and deep acceptor-like trap states in bulk

For fully-depleted polycrystalline silicon thin film transistors including both tail and deep acceptor-like trap states in the bulk and interface charges, a channel-potential-based surface potential model (including front and back surface potential) and a turn-on DC channel-potential-based drain current model are proposed with the effect of the back surface potential considered. Firstly, a channel-potential-based surface potential model is obtained by introducing a channel-potential-based front and back surface potential equation and a channel-potential-based equation describing the coupling effect of the front and back surface potential. Contributions of active acceptors, electrons and trapped charges are all taken into account in this coupling effect. Moreover, by integrating the electron concentration, vertically to the front poly-Si/oxide interface, in the inversion layer, using the average electric field concept and considering the effect of channel potential in the potential of the inversion layer’s ending point, the areal density of the inversion charge is deduced. Furthermore, a channel-potential-based drain current model, avoiding the double numerical integration, is developed with the merit of relative simplification in calculation. By using recursive Simpson rules, this drain current model is calculated by numerical integration with the examining condition. And the above proposed models are verified by 2D-device simulation from MEDICI.

Влияние глубоких уровней дислокаций в гетероэпитаксиальных InGaAs/GaAs и GaAsSb/GaAs p-i-n-структурах на время релаксации неравновесных носителей

The results of an experimental study of the capacitance–voltage ( C – V ) characteristics and deep-level transient spectroscopy (DLTS) spectra of p ^+– p ^0– i – n ^0 homostructures based on undoped dislocationfree GaAs layers and InGaAs/GaAs and GaAsSb/GaAs heterostructures with homogeneous networks of misfit dislocations, all grown by liquid-phase epitaxy (LPE), are presented. Deep-level acceptor defects identified as HL 2 and HL 5 are found in the epitaxial p ^0 and n ^0 layers of the GaAs-based structure. The electron and hole dislocation-related deep levels, designated as, respectively, ED 1 and HD 3, are detected in InGaAs/GaAs and GaAsSb/GaAs heterostructures. The following hole trap parameters: thermal activation energies ( E _ t ), capture cross sections (σ_ p ), and concentrations ( N _ t ) are calculated from the Arrhenius dependences to be E _ t = 845 meV, σ _ p = 1.33 × 10^–12 cm^2, N _ t = 3.80 × 10^14 cm^–3 for InGaAs/GaAs and E _ t = 848 meV, σ _ p = 2.73 × 10^–12 cm^2, N _ t = 2.40 × 10^14 cm^–3 for GaAsSb/GaAs heterostructures. The concentration relaxation times of nonequilibrium carriers are estimated for the case in which dislocation-related deep acceptor traps are involved in this process. These are 2 × 10^–10 s and 1.5 × 10^–10 s for, respectively, the InGaAs/GaAs and GaAsSb/GaAs heterostructures and 1.6 × 10^–6 s for the GaAs homostructures.

Electrical Instability of CdTe:Si Crystals

Results of Hall effect measurements of cadmium telluride crystals, doped by silicon (dopant concentration in the melt was 1018 - 1019 cm-3), allowed to classify the studied samples and the conditions under which probably the definite crystal and impurity states are realized. We have found the distinction between 3 type of CdTe:Si crystals: (1) low-resistance p-type crystals with shallow acceptors, in which Si impurity is localized mainly in the large inclusions; (2) semi-insulating crystal with deep acceptors and submicron size dopant precipitates that are source/drain for interstitials Sii - shallow donors; and (3) low-resistance crystals in which the n-type conductivity is provided by shallow donors: Sii (and/or SiCd). Therefore the silicon is responsible for n-type conductivity of doped samples, introducing as a donor Siі and provides semi-insulating state by forming deep acceptor complexes (SiCd-VCd2-)- with (Еv + 0.65 eV). Besides, the submicron silica precipitates, that have a tendto"dissolution" at relatively low temperatures, can act aselectricallyactive centers.