A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

Origins and minimization of intermodulation distortion in a pseudo-differential CMOS beamforming receiver

This paper studies how nonlinear distortion is generated in the combination of an inverter-based low-noise amplifier and a passive mixer. The dominant nonlinearity appears to be the quadratic $$V_{gs}V_{ds}$$ V gs V ds mixing term in the passive mixer that first causes low-frequency IM2 and then upconverts it to IM3. Adding a common-mode feedback (CMFB) cancels the IM2 in a pseudo-differential structure, and hence also reduces the IM3 caused by the cascaded second order nonlinearities significantly. The effect of CMFB gain, bandwidth and linearity were analyzed, and it is concluded that from the linearity point of view, the feedback circuit does not have to be very wideband since the dominant distortion products originate from baseband. Finally, the paper takes a look at the spurious tones rising in the mixing, and how to extend the analysis to include the actual frequency translation effect.

TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS

System-on-Chip (SoC) is one of the main driving forces that have been re-shaping the consumer electronics industry. The SoC alternative to conventional systems design is growing in popularity as the device packing densi escalates due to the evolution of semiconductor technology. Moreover, the decrease in semiconductor feature size is permitting the increase of clock frequencies and component operating speed. These advancements necessitate the integration of system components due to package parasitics and lengthy interconnect. Furthermore, SoC devices offer a cheaper and more compact solution to the consumer electronics industry.An integrated mixed-signal test core approach to SoC data acquisition is a valued alternate solution to many of the problems involving conventional test. One such test core data conversion architecture incorporates a sub-sampling algorithm known as the multipass method of digitization. This method occupies a very small silicon area in exchange for an increased data conversion time. Time-interleaved test core digitizers provide the capability to reduce test time, increase sampling frequency and increase signal bandwidth. As an implicit result of this compact circuit and multipass processing methodology, significant reductions in noise and spurious tones are observed.

Analysis of the frequency conversion of spurious tones in frequency dividers and development of an event-driven model for system simulations

This paper presents a frequency domain analysis of spurious tones in frequency dividers. The results of the analysis are used to develop an event-driven model for system simulations which work entirely in the frequency domain. The proposed approach is able to provide a fast and accurate model in a SystemVerilog/C++ environment which takes the frequency conversion effects of the spurious tones into account. A virtual prototype which includes the model was simulated and due to the fast simulation speed it was possible to determine the influence of spurious tones on the bit error rate in a complex receive scenario.