40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

All-optical Frequency Divider using TOAD based D-Flip-Flop

From the last few decades the optical communication has been established as much easier process than electrical communication. Many optical proposed circuits have already been suggested in many fields in support of this. The optical communication circuits demand frequency dividers capable of operating well above 10 GHz. Here, an all-optical frequency divider using terahertz optical asymmetric demultiplexer (TOAD) based D-flip-flop is proposed in the optical domain in a configuration exactly like the standard electronic setup. It presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology with satisfactory performance. The proposed all-optical frequency division scheme has been theoretically demonstrated in this paper. In this scheme the input and output binary digits are expressed as the presence (1) and the absence (0) of the light pulses. The performance of this proposed optical realization is evaluated by numerical simulation that confirms its feasibility in terms of the choice of the critical parameters.

The use of frequency converters on three-circuit ferroresonant circuits

In this paper, the processes of formation of low-frequency currents in the circuits of ferromagnetic oscillations are analyzed, and the theory of the formation of secondary amplitude frequencies of soft excitation of parallel and series-connected ferroresonant chains is developed. Based on this, considering the use of frequency dividers in the irrigation system shown in Figure 1, it is possible to carry out experiments on the study of multi-circuit frequency dividers. Therefore, the study of spontaneous (soft) vibration processes in multi-circuit ferroresonant electric circuits of periodic changes in the parameters of a ferromagnetic element generated by the resulting harmonic oscillations (HA) and their development and application of improved sources of harmonic signals for telecontrol of the system in power lines, switchgears and drainage networks.

Application of an auto-parametric circuit for controlling thyristor converters

This article discusses the issues of excitation of second-order subharmonic oscillations, in circuits representing a two-core electro-ferromagnetic circuit with a capacitive load, in order to use it to control the states of thyristors, frequency converters. The stability of the solutions of the equations of the two-core chain is investigated. Recommendations are given for obtaining stable subharmonic oscillations of the order 1/2 f when using these circuits as a control element of thyristor frequency dividers by two.