An effective approach to automatic functional processor test generation for small-delay faults

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date.2014.140 ◽

2014 ◽

Cited By ~ 6

Author(s):

Andreas Riefert ◽

Lyl Ciganda ◽

Matthias Sauer ◽

Paolo Bernardi ◽

Matteo Sonza Reorda ◽

...

Keyword(s):

Test Generation ◽

Delay Faults ◽

Small Delay

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An effective approach to automatic functional processor test generation for small-delay faults

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date2014.140 ◽

2014 ◽

Cited By ~ 1

Author(s):

Andreas Riefert ◽

Lyl Ciganda ◽

Matthias Sauer ◽

Paolo Bernardi ◽

Matteo Sonza Reorda ◽

...

Keyword(s):

Test Generation ◽

Delay Faults ◽

Small Delay

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An Automatic Test Generation Method for Crosstalk Delay Faults Using Modified FAN Algorithm

Test Generation of Crosstalk Delay Faults in VLSI Circuits ◽

10.1007/978-981-13-2493-2_4 ◽

2018 ◽

pp. 57-77

Author(s):

S. Jayanthy ◽

M. C. Bhuvaneswari

Keyword(s):

Test Generation ◽

Delay Faults ◽

Automatic Test Generation ◽

Automatic Test ◽

Fan Algorithm

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A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741773 ◽

2019 ◽

Author(s):

Chao-Jun Shang ◽

Cheng-Hung Wu ◽

Kuen-Jong Lee ◽

Yu-Hsiang Chen

Keyword(s):

Test Generation ◽

Fault Model ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e96.d.1323 ◽

2013 ◽

Vol E96.D (6) ◽

pp. 1323-1331

Author(s):

Yoshinobu HIGAMI ◽

Hiroshi TAKAHASHI ◽

Shin-ya KOBAYASHI ◽

Kewal K. SALUJA

Keyword(s):

Test Generation ◽

Delay Faults ◽

Test Environment

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Cited By ~ 30

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785514 ◽

2010 ◽

Cited By ~ 1

Author(s):

Bo Yao ◽

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Transition Path

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SIMULATION BASED LOW POWER TEST GENERATION FOR CROSSTALK DELAY FAULTS

International Journal of Modelling and Simulation ◽

10.2316/journal.205.2011.3.205-5524 ◽

2011 ◽

Vol 31 (3) ◽

Author(s):

Jayanthy Soundararajan ◽

Bhuvaneswari M. Chinnadurai

Keyword(s):

Low Power ◽

Test Generation ◽

Delay Faults ◽

Power Test ◽

Low Power Test ◽

Simulation Based

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Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.81 ◽

2007 ◽

Cited By ~ 2

Author(s):

Rajsekhar Adapa ◽

Edward Flanigan ◽

Spyros Tragoudas ◽

Michael Laisne ◽

Hailong Cui ◽

...

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.51 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Resistive Bridges

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Cited By ~ 12

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

Automatic Test

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