scholarly journals FSMD-Based Hardware Accelerators for FPGAs

10.5772/36932 ◽  
2012 ◽  
Author(s):  
Nikolaos Kavvadias ◽  
Vasiliki Giannakopoulou ◽  
Kostas Masselos
Keyword(s):  
Hardware Accelerators

Hardware accelerators for CAD

1989 ◽  
Vol 6 (3) ◽  
pp. 77
Author(s):  
A.P. Ambler
Keyword(s):  
Hardware Accelerators

scholarly journals Leveraging Edge Intelligence for Video Analytics in Smart City Applications

Information ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 14
Author(s):  
Aluizio Rocha Neto ◽  
Thiago P. Silva ◽  
Thais Batista ◽  
Flávia C. Delicato ◽  
Paulo F. Pires ◽  
...  
Keyword(s):  
Distributed System ◽  
Smart City ◽  
Large Scale ◽  
Facial Recognition ◽  
Public Spaces ◽  
Hardware Accelerators ◽  
Video Streams ◽  
Video Analytics ◽  
Learning Tasks ◽  
Naive Approach

In smart city scenarios, the huge proliferation of monitoring cameras scattered in public spaces has posed many challenges to network and processing infrastructure. A few dozen cameras are enough to saturate the city’s backbone. In addition, most smart city applications require a real-time response from the system in charge of processing such large-scale video streams. Finding a missing person using facial recognition technology is one of these applications that require immediate action on the place where that person is. In this paper, we tackle these challenges presenting a distributed system for video analytics designed to leverage edge computing capabilities. Our approach encompasses architecture, methods, and algorithms for: (i) dividing the burdensome processing of large-scale video streams into various machine learning tasks; and (ii) deploying these tasks as a workflow of data processing in edge devices equipped with hardware accelerators for neural networks. We also propose the reuse of nodes running tasks shared by multiple applications, e.g., facial recognition, thus improving the system’s processing throughput. Simulations showed that, with our algorithm to distribute the workload, the time to process a workflow is about 33% faster than a naive approach.

scholarly journals Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators

2018 ◽  
Vol 106 (11) ◽  
pp. 2040-2055 ◽  
Author(s):  
Jack Dongarra ◽  
Mark Gates ◽  
Jakub Kurzak ◽  
Piotr Luszczek ◽  
Yaohung M. Tsai
Keyword(s):  
Linear Algebra ◽  
Hardware Accelerators ◽  
Dense Linear Algebra
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