scholarly journals High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 62207-62217
Author(s):  
Morgan Ledwon ◽  
Bruce F. Cockburn ◽  
Jie Han
Keyword(s):  
High Throughput ◽  
High Level Synthesis ◽  
Hardware Accelerators ◽  
High Level

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

scholarly journals FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2024
Author(s):  
Julián Caba ◽  
Fernando Rincón ◽  
Jesús Barba ◽  
José Antonio de la Torre ◽  
Juan Carlos López
Keyword(s):  
Software Industry ◽  
Design Flow ◽  
High Level Synthesis ◽  
Reconfigurable Systems ◽  
Hardware Accelerators ◽  
Testing Environment ◽  
Development Life Cycle ◽  
Verification Process ◽  
Specialized Hardware ◽  
High Level

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

PHIDEO: High-level synthesis for high throughput applications

1995 ◽  
Vol 9 (1-2) ◽  
pp. 89-104 ◽  
Author(s):  
J. L. Van Meerbergen ◽  
P. E. R. Lippens ◽  
W. F. J. Verhaegh ◽  
A. Van Der Werf
Keyword(s):  
High Throughput ◽  
High Level Synthesis ◽  
High Level
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