Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

Rehan Maroofi;  Nitnaware;  Limaye

doi:10.5121/vlsic.2011.2309

Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2309 ◽

2011 ◽

Vol 2 (3) ◽

pp. 111-118 ◽

Cited By ~ 1

Author(s):

Rehan Maroofi ◽

Nitnaware ◽

Limaye

Keyword(s):

Network On Chip ◽

Efficient Design ◽

On Chip ◽

Area Efficient

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Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers

2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems ◽

10.1109/ecbs.2010.21 ◽

2010 ◽

Cited By ~ 8

Author(s):

Khalid Latif ◽

Tiberiu Seceleanu ◽

Hannu Tenhunen

Keyword(s):

Network On Chip ◽

Efficient Design ◽

On Chip ◽

Area Efficient

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An Low-Power Area-Efficient Routing Analysis and Optimization for a Fat Tree-Based Optical Network-on-Chip (ONoC) Architectures

Sensor Letters ◽

10.1166/sl.2018.4033 ◽

2018 ◽

Vol 16 (11) ◽

pp. 862-876 ◽

Cited By ~ 4

Author(s):

R. Poovendran ◽

S. Sumathi

Keyword(s):

Low Power ◽

Optical Network ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681443 ◽

2010 ◽

Cited By ~ 13

Author(s):

Zhiyao Joseph Yang ◽

Akash Kumar ◽

Yajun Ha

Keyword(s):

Network On Chip ◽

Dynamically Reconfigurable ◽

On Chip ◽

Spatial Division Multiplexing ◽

Area Efficient

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An Area-Efficient FPGA Implementation of Network-on-Chip (NoC) Router Architecture for Optimized Multicore-SoC Communication

Sensor Letters ◽

10.1166/sl.2018.3985 ◽

2018 ◽

Vol 16 (7) ◽

pp. 552-560 ◽

Cited By ~ 5

Author(s):

R. Poovendran ◽

S. Sumathi

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

Router Architecture ◽

On Chip ◽

Area Efficient

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EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2018.00070 ◽

2018 ◽

Cited By ~ 1

Author(s):

Mubashir Hussain ◽

Amin Malekpour ◽

Hui Guo ◽

Sri Parameswaran

Keyword(s):

Energy Efficient ◽

Network On Chip ◽

Hardware Trojan ◽

Efficient Design ◽

Hardware Trojan Detection ◽

Trojan Detection ◽

Energy Efficient Design ◽

On Chip

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FPGA based design of area efficient router architecture for Network on Chip (NoC)

2016 International Conference on Computing, Communication and Automation (ICCCA) ◽

10.1109/ccaa.2016.7813980 ◽

2016 ◽

Author(s):

Mayank Kumar ◽

Kishore Kumar ◽

Sanjiv Kumar Gupta ◽

Yogendera Kumar

Keyword(s):

Network On Chip ◽

Router Architecture ◽

On Chip ◽

Area Efficient

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Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems - ANCS '07 ◽

10.1145/1323548.1323561 ◽

2007 ◽

Cited By ~ 7

Author(s):

Avinash Kodi ◽

Ashwini Sarathy ◽

Ahmed Louri

Keyword(s):

Low Power ◽

Communication Channel ◽

Network On Chip ◽

Adaptive Communication ◽

On Chip ◽

Area Efficient

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3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Microprocessors and Microsystems ◽

10.1016/j.micpro.2011.04.001 ◽

2011 ◽

Vol 35 (5) ◽

pp. 484-495 ◽

Cited By ~ 8

Author(s):

Licheng Xue ◽

Feng Shi ◽

Weixing Ji ◽

Haroon-Ur-Rashid Khan

Keyword(s):

Low Power ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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MRBS: An Area-Efficient Multicast Router for Network-on-Chip using Buffer Sharing

IEEE Access ◽

10.1109/access.2021.3137218 ◽

2021 ◽

pp. 1-1

Author(s):

Min Chae Yang ◽

Young Sik Lee ◽

Tae Hee Han

Keyword(s):

Network On Chip ◽

Buffer Sharing ◽

On Chip ◽

Area Efficient

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An area efficient network on chip architecture using high performance pipelines FIFO technique

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) ◽

10.1109/iceice.2017.8191936 ◽

2017 ◽

Cited By ~ 1

Author(s):

S. Sariga ◽

C. Nandagopal

Keyword(s):

High Performance ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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