3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Licheng Xue; Feng Shi; Weixing Ji; Haroon-Ur-Rashid Khan

doi:10.1016/j.micpro.2011.04.001

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Microprocessors and Microsystems ◽

10.1016/j.micpro.2011.04.001 ◽

2011 ◽

Vol 35 (5) ◽

pp. 484-495 ◽

Cited By ~ 8

Author(s):

Licheng Xue ◽

Feng Shi ◽

Weixing Ji ◽

Haroon-Ur-Rashid Khan

Keyword(s):

Low Power ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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An Low-Power Area-Efficient Routing Analysis and Optimization for a Fat Tree-Based Optical Network-on-Chip (ONoC) Architectures

Sensor Letters ◽

10.1166/sl.2018.4033 ◽

2018 ◽

Vol 16 (11) ◽

pp. 862-876 ◽

Cited By ~ 4

Author(s):

R. Poovendran ◽

S. Sumathi

Keyword(s):

Low Power ◽

Optical Network ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems - ANCS '07 ◽

10.1145/1323548.1323561 ◽

2007 ◽

Cited By ~ 7

Author(s):

Avinash Kodi ◽

Ashwini Sarathy ◽

Ahmed Louri

Keyword(s):

Low Power ◽

Communication Channel ◽

Network On Chip ◽

Adaptive Communication ◽

On Chip ◽

Area Efficient

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Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures

2009 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2009.4796432 ◽

2009 ◽

Cited By ~ 8

Author(s):

Avinash Karanth Kodi ◽

Ashwini Sarathy ◽

Ahmed Louri ◽

Janet Wang

Keyword(s):

Low Power ◽

Network On Chip ◽

On Chip ◽

Area Efficient

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An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

Concurrency and Computation Practice and Experience ◽

10.1002/cpe.4760 ◽

2018 ◽

Vol 31 (14) ◽

Cited By ~ 1

Author(s):

R. Poovendran ◽

S. Sumathi

Keyword(s):

Low Power ◽

High Performance ◽

Network On Chip ◽

Routing Design ◽

On Chip ◽

Area Efficient

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Design of R3TOS based reliable low power network on chip

2017 Seventh International Conference on Emerging Security Technologies (EST) ◽

10.1109/est.2017.8090423 ◽

2017 ◽

Author(s):

N Poornima ◽

Seetharaman Gopalakrishnan ◽

Tughrul Arsalan ◽

T. N. Prabakar ◽

M. Santhi

Keyword(s):

Low Power ◽

Network On Chip ◽

Power Network ◽

On Chip

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Low-power mapping algorithm for three-dimensional network-on-chip based on diversity-controlled quantum-behaved particle swarm optimization

Journal of Algorithms & Computational Technology ◽

10.1177/1748301816649070 ◽

2016 ◽

Vol 10 (3) ◽

pp. 176-186 ◽

Cited By ~ 3

Author(s):

Cui Huang ◽

Dakun Zhang ◽

Guozhi Song

Keyword(s):

Particle Swarm Optimization ◽

Low Power ◽

Three Dimensional ◽

Particle Swarm ◽

Network On Chip ◽

Swarm Optimization ◽

Mapping Algorithm ◽

Dimensional Network ◽

On Chip ◽

Power Mapping

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Low power, high performance current mode transceiver for Network-on-Chip communication

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies ◽

10.1109/icsccn.2011.6024548 ◽

2011 ◽

Author(s):

V. Mohana Vidya ◽

R. Thilagavathy ◽

M. Bhaskar

Keyword(s):

Low Power ◽

High Performance ◽

Current Mode ◽

Network On Chip ◽

On Chip

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A low-power wireless-assisted multiple network-on-chip

Microprocessors and Microsystems ◽

10.1016/j.micpro.2018.09.001 ◽

2018 ◽

Vol 63 ◽

pp. 104-115 ◽

Cited By ~ 1

Author(s):

Mohammad Baharloo ◽

Ahmad Khonsari

Keyword(s):

Low Power ◽

Network On Chip ◽

Multiple Network ◽

On Chip

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Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2309 ◽

2011 ◽

Vol 2 (3) ◽

pp. 111-118 ◽

Cited By ~ 1

Author(s):

Rehan Maroofi ◽

Nitnaware ◽

Limaye

Keyword(s):

Network On Chip ◽

Efficient Design ◽

On Chip ◽

Area Efficient

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A low power network interface for network on chip

Eighth International Multi-Conference on Systems, Signals & Devices ◽

10.1109/ssd.2011.5767464 ◽

2011 ◽

Cited By ~ 11

Author(s):

W Chouchene ◽

B Attia ◽

A Zitouni ◽

N Abid ◽

R Tourki

Keyword(s):

Low Power ◽

Network On Chip ◽

Network Interface ◽

Power Network ◽

On Chip

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