FPGA based design of area efficient router architecture for Network on Chip (NoC)

2016 ◽  
Author(s):  
Mayank Kumar ◽  
Kishore Kumar ◽  
Sanjiv Kumar Gupta ◽  
Yogendera Kumar
Keyword(s):  
Network On Chip ◽  
Router Architecture ◽  
On Chip ◽  
Area Efficient

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

Designing fault-tolerant network-on-chip router architecture

2010 ◽  
Vol 97 (10) ◽  
pp. 1181-1192 ◽  
Author(s):  
Ashkan Eghbal ◽  
Pooria M. Yaghini ◽  
H. Pedram ◽  
H. R. Zarandi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document