An Area-Efficient FPGA Implementation of Network-on-Chip (NoC) Router Architecture for Optimized Multicore-SoC Communication

2018 ◽  
Vol 16 (7) ◽  
pp. 552-560 ◽  
Author(s):  
R. Poovendran ◽  
S. Sumathi
Keyword(s):  
Network On Chip ◽  
Fpga Implementation ◽  
Router Architecture ◽  
On Chip ◽  
Area Efficient

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

Designing fault-tolerant network-on-chip router architecture

2010 ◽  
Vol 97 (10) ◽  
pp. 1181-1192 ◽  
Author(s):  
Ashkan Eghbal ◽  
Pooria M. Yaghini ◽  
H. Pedram ◽  
H. R. Zarandi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip
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