scholarly journals On a Predictive Scheme of Slow Photoconductive Gain Evolution in Epitaxial Layer/Substrate Optoelectronic Nanodevices

2011 ◽  
Vol 01 (02) ◽  
pp. 32-34 ◽  
Author(s):  
G. E. Zardas ◽  
C. J. Aidinis ◽  
E. A. Anagnostakis ◽  
Ch. I. Symeonides
Author(s):  
Pham V. Huong ◽  
Stéphanie Bouchet ◽  
Jean-Claude Launay

Microstructure of epitaxial layers of doped GaAs and its crystal growth dynamics on single crystal GaAs substrate were studied by Raman microspectroscopy with a Dilor OMARS instrument equipped with a 1024 photodiode multichannel detector and a ion-argon laser Spectra-Physics emitting at 514.5 nm.The spatial resolution of this technique, less than 1 μm2, allows the recording of Raman spectra at several spots in function of thickness, from the substrate to the outer deposit, including areas around the interface (Fig.l).The high anisotropy of the LO and TO Raman bands is indicative of the orientation of the epitaxial layer as well as of the structural modification in the deposit and in the substrate at the interface.With Sn doped, the epitaxial layer also presents plasmon in Raman scattering. This fact is already very well known, but we additionally observed that its frequency increases with the thickness of the deposit. For a sample with electron density 1020 cm-3, the plasmon L+ appears at 930 and 790 cm-1 near the outer surface.


2019 ◽  
Vol 3 (9) ◽  
Author(s):  
Victor Ukleev ◽  
Mikhail Volkov ◽  
Alexander Korovin ◽  
Thomas Saerbeck ◽  
Nikolai Sokolov ◽  
...  
Keyword(s):  

2007 ◽  
Vol 556-557 ◽  
pp. 153-156
Author(s):  
Chi Kwon Park ◽  
Gi Sub Lee ◽  
Ju Young Lee ◽  
Myung Ok Kyun ◽  
Won Jae Lee ◽  
...  

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. The blue light emission was successfully observed on a PN diode structure fabricated with the p-type SiC epitaxial layer. Furthermore, 4H-SiC MESFETs having a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized.


2004 ◽  
Vol 70 (20) ◽  
Author(s):  
H. Wen ◽  
Zh. M. Wang ◽  
J. L. Shultz ◽  
B. L. Liang ◽  
G. J. Salamo
Keyword(s):  

2017 ◽  
Vol 897 ◽  
pp. 287-290 ◽  
Author(s):  
Matthias Kocher ◽  
Michael Niebauer ◽  
Mathias Rommel ◽  
Volker Haeublein ◽  
Anton J. Bauer

Point contact current voltage (PCIV) measurements were performed on 4H-SiC samples, both for n- an p-doped epitaxial layers as well as samples with rather shallow doping profiles realized by N- or Al-implantation in a range from 1016 cm-3 to 1019 cm-3. Surface preparation and measurement parameters were investigated in order to determine their influence on the measured resistance profiles. Furthermore depth profile measurements were performed on both an epitaxial layer as well as on implanted samples. These depth profiles could be measured reproducibly and showed good agreement with expected profiles for Al-implanted samples as well as for epitaxial layer whereas for N-implanted samples deviations between measured and expected profiles could be observed. It could be proven that PCIV profiling technique is a promising method for characterizing doped profiles in 4H-SiC, especially on Al-implanted samples.


2003 ◽  
Vol 336 (3-4) ◽  
pp. 344-348 ◽  
Author(s):  
Xinyun Xie ◽  
Weili Liu ◽  
Qing Lin ◽  
Chuanling Men ◽  
Chenglu Lin

2008 ◽  
Vol 600-603 ◽  
pp. 525-528
Author(s):  
Laurent Ottaviani ◽  
Michel Kazan ◽  
Pierre M. Masri ◽  
Thierry Sauvage

Metal impurities are known to degrade dramatically the performances of silicon-based devices, even at concentrations as low as 1012 cm-3. A specific process, named proximity gettering, has been optimised by some authors in order to reduce the influence of these impurities [1]. This process consists in the building of a favourable impurity trapping zone in a non-active area of the device, by introducing implantation defects. This paper reports on the application of introducing such gettering sites as an approach to control phonon properties in 4H-SiC epilayer, and increase the thermal conductivity.


AIP Advances ◽  
2012 ◽  
Vol 2 (1) ◽  
pp. 012177 ◽  
Author(s):  
Yoshinobu Aoyagi ◽  
Misaichi Takeuchi ◽  
Sohachi Iwai ◽  
Hideki Hirayama

Sign in / Sign up

Export Citation Format

Share Document