Electromigration Performance of Fine-Pitch Copper Pillar Interconnections

2012 ◽  
Vol 2012 (1) ◽  
pp. 001018-001025
Author(s):  
Ahmer Syed ◽  
Christopher J. Berry ◽  
Karthikeyan Dhandapani ◽  
Patrick Thompson ◽  
Seung-Hyun Chae

The miniaturization trend in electronic packaging continues to drive smaller and smaller chip-to-substrate interconnections with no reduction in IC operating temperature or device power in sight. These two factors (current density and temperature) make the electromigration lifetime of chip-to-package interconnections a critical consideration in package design. Of particular interest these days are the “fine pitch copper pillar” structures due to their very small size (30um dia or less). This paper presents interconnection lifetime and metallurgical data on the same which demonstrates the extreme robustness of these joints due largely to their reaching a fully reacted state in which no free solder exists in the conduction path thus providing electromigration performance like that of the base copper and intermetallic compounds. Joint resistance trends observed during stress testing are also discussed.

2007 ◽  
Vol 990 ◽  
Author(s):  
Yi Li ◽  
Myung Jin Yim ◽  
Kyung Sik Moon ◽  
ChingPing Wong

ABSTRACTIn this paper, a novel nano-scale conductive film which combines the advantages of both traditional anisotropic conductive adhesives/films (ACAs/ACFs) and nonconductive adhesives/films (NCAs/NCFs) is introduced and developed for next generation high performance ultra-fine pitch packaging applications. This novel interconnect film possesses the properties of electrical conduction along the z-direction with relatively low bonding pressure (ACF-like) and the ultra-fine pitch (< 100 nm) capability (NCF-like). Unlike typical ACF which requires 1–5 vol% of conductive fillers, the novel nano-scale conductive film only needs less than 0.1 vol% conductive fillers to achieve good electrical conductance in the z direction. The nano-scale conductive film also allows a lower bonding pressure than NCF to achieve a much lower joint resistance (over two orders of magnitude lower than typical ACF joints) and higher current carrying capability. With low temperature sintering of nano-silver fillers, the joint resistance of the nano-scale conductive film could be as low as 10−5 Ohm, even lower than the NCF and lead-free solder joints. The reliability of the nano-scale conductive film after high temperature and humidity test (85°C/85%RH) was also improved compared to the NCF joints. As such, a high performance, fine pitch conductive film was developed.


2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.


2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.


2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Tong An ◽  
Fei Qin

This paper investigates the formation and the growth of the intermetallic compound (IMC) layer at the interface between the Sn3.0Ag0.5Cu Pb-free solder and the Cu substrate during isothermal aging at 150 °C. We measure the thickness of the IMC layer and the roughness of the solder/IMC interface, and these two factors are assumed to control the tensile behavior of the solder joints. First, it utilizes the tensile tests of the aged solder joints for analyzing the effect of the IMC growth on the tensile behavior of the solder joints. Then, the microcracking behavior of the IMC layer is investigated by finite element method (FEM). In addition, qualitative numerical simulations are applied to study the effect of the IMC layer thickness and the solder/IMC interfacial roughness on the overall response and the failure mode of solder joints. The experimental results indicate that when the aging time increases, both the thickness and the roughness of the IMC layer have a strong influence on the strength and the failure mode of solder joints. The numerical simulation results suggest that the overall strength of solder joints is reduced when the IMC layer is thick and the solder/IMC interface is rough, and the dominant failure mode migrates to the microcracks within the IMC layer when the IMC layer is thick and the solder/IMC interface is flat.


Author(s):  
Deepak Manjunath ◽  
Satyanarayan Iyer ◽  
Shawn Eckel ◽  
Purushothaman Damodaran ◽  
Krishnaswami Srihari

Fine pitch leadless components, such as Ball Grid Arrays (BGAs) and Chip-Scale Packages (CSPs), are increasingly used in modern day circuitry to aid miniaturization. Assembling these surface mount components using lead-free solder pastes has been a subject of interest for the past several years. Reworking a BGA is complicated as the solder joints are hidden underneath the component. The process window available for the rework process is very narrow and there are number of other critical factors, which complicate and affect the repeatability of the rework process. Consequently, the primary objective of this research endeavor is to develop a reliable and a repeatable process to rework lead-free fine pitch BGAs. The process steps to rework a BGA are component removal, site redressing, solder paste/flux deposition, component replacement and reflow. This experimental study evaluates a number of alternatives for several rework process steps during the course of developing a reliable and repeatable rework process. Two alternatives for site redressing namely, (i) copper wick with soldering iron, and (ii) vacuum de-soldering methods are evaluated. Similarly the application of solder paste versus gel flux is compared. A localized reflow method for replacing the component at the SRT machine is developed and it is compared with forced convection in reflow oven. The pros and cons of using the two reflow methods and the effect of multiple reflows on solder joint reliability is discussed in the paper. A reliability study was conducted on the samples and the results are presented to compare the various alternatives.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001016-001038
Author(s):  
Ryuji Uesugi ◽  
Hironori Uno ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda ◽  
Hiroki Muraoka ◽  
...  

We have successfully developed super fine lead-free and low alpha solder powder, which contains more than two elements by the method of wet chemical reduction. The size (D50) of super fine powder is around 2–3 micrometer to meet finer pitch assembly in the near future. This new method made it available to synthesize various compositions of solder powder like Sn-Ag, Sn-Cu, Sn-Ag-Cu, etc. Also, this method achieves very high yield compared to a gas atomization method. A solder paste for printing method composed of the fine solder powder has a superior printing ability because of the unique powder shape. The powder shows anisotropic shape, and it can make printed figure excellent after printing without bridge and coplanarity issues for finer pitch applications. With our super fine solder paste, we will be ready for &lt;100um pitch of solder bumps which will come in a few years. Furthermore, the super fine powder is applied to the Cu pad pre-coat. The solder paste for pre-coat composed of the super fine powder shows an excellent coverage and solders flatness on the outer pad after reflow.


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