Development of high-yield and high-reliability design for high-performance ultra large scale 3DLSI processor

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-31 ◽  
Author(s):  
Hideki Kitada
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Yield Loss ◽  
High Reliability ◽  
Signal Transmission ◽  
High Yield ◽  
Design Technology ◽  
Large Current ◽  
Fine Pitch ◽  
3D Packaging

With LSI micro-fabrication technology reaching its scaling limits, miniaturizing LSIs based on Moore's Law is unable to satisfy the CPU/memory module performance for high-speed, low-power, high-end servers, an alternative integration technology such as three-dimensional integration (3DI) is becoming mainstream. With the development of 3D stacked high-performance processors, specifications that excel in power consumption (200 to 300 W), heat generation, number of electrodes and large die area are required, necessitating a major technical leap from the conventional 3D packaging technologies. A guarantee of reliability and the yield loss is very severe, because of the high-performance processor's needing 30 times or more the both die area and the number of pins compared with the combinational high band width memory stacking. We were the first to verify 3D logic device operation by integrating the following technologies: through-silicon via (TSV) technologies, in which signals are connected in the shortest distance between a top and bottom stacked ultra-large die area processor die; novel redundancy signal transmission design technology; super multi-pins connection technology for high-yield signal transmission with high bandwidth; and high reliability solder joint materials considering power integrity (PI) between stacked dies. To achieve the high-yield TSV connection, the TSV redundant circuit was designed and installed into the stack dies due to the difficulty of the avoidance of defect density (D0) increasing such as large die area. Novel logic macro design with one redundant TSV for 16 signal node enabled the accurate switching selection to redundant defective TSV by using the execution of a pre-test sequence to find bad TSV. In addition, a redundant logic circuit of top and bottom interconnect is a design that gives control signal the redundancy. As a result, the higher operation guarantee was given to the operation execution of controlling circuit. This redundant circuit design technology demonstrated without yield loss of TSV interconnect. For high-reliability fine pitch bump (40-μm pitch) and 10-μm TSV interconnect formation technologies, a large-current, high-heat dissipation and high-precision stacking technology were required. We have developed a process technology for fine-pitch micro bump junctions supporting large current and high-precision I/O bumps stacking dies with 200,000 or more pins using by Ni-Sn intermetallic compound (IMC) solder materials. We also have developed a high accuracy of large die stacking process to be used in fine TSV in which large amounts of current flow and connection terminal sections on dies, achieving stable supply of 300-Watt-class power consumption. Compared with the current density for a 10-year guaranteed lifetime, the case of IMC alloy joining achieves a current density resistance of 4 times more than that of conventional Sn-Ag solder materials, and this has proven to be effective for a high-performance processor. By developing 3DLSI packaging technology compatible with ultra large dies for a high-performance processor and overcoming the issue of yield and reliability, we have achieved a redundancy design technology and micro bump materials of high-yield at product level stacked logic processor with over 750 mm square as full reticle shot size. In this paper, we will discuss the important key redundancy TSV design method and micro bump material technologies; in 3D packaging technology for realizing high-performance ultra large scale processor.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000930-000959
Author(s):  
Wael Zohni ◽  
Rajesh Katkar ◽  
Rey Co ◽  
Rizza Cizek
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Volume ◽  
Third Party ◽  
High Yield ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Manufacturing Readiness

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

scholarly journals Study on Design of Novel Function/Structure Integration Mounting Plate for Space borne SAR Antenna for Wireless Communication

2021 ◽  
Vol 2083 (2) ◽  
pp. 022095
Author(s):  
Shouli Jiang ◽  
Jia Li ◽  
Tongtong Leng ◽  
Rui Xiao ◽  
Zihao Yang ◽  
...  
Keyword(s):  
High Precision ◽  
Large Scale ◽  
Heat Dissipation ◽  
Control Function ◽  
High Reliability ◽  
Signal Transmission ◽  
Transmission Function ◽  
Low Frequency ◽  
Thermal Control ◽  
Antenna Structure

Abstract A novel lightweight and high-precision synthetic aperture radar (SAR) antenna mounting plate scheme based on functional structure integration technology is proposed. The thermal control function, high and low frequency blind insertion signal transmission function of the system are combined with the antenna structure to greatly reduce the size and weight of SAR antenna. The design verification of a high-density integrated SAR antenna mounting plate breaks through the key process technologies such as accurate splicing of multiple interfaces of the mounting plate, highly reliable cementation of non-uniform honeycomb and large-scale warpage control, and solves the key technical difficulties of high precision, high temperature and high reliability. The results show that the antenna mounting plate (size 649mm × 430mm) the overall flatness is better than 0.28mm, the thickness limit dimension deviation is less than 0.1mm, and the temperature consistency is less than 1.8°C. It can meet the requirements of lightweight, structural stiffness and strength, RF blind plug connection and heat dissipation for space borne SAR antenna.

scholarly journals Automated Cytogenetic Biodosimetry at Population-Scale

2019 ◽  
Author(s):  
PK Rogan ◽  
R Lu ◽  
E Mucaki ◽  
S Ali ◽  
B Shirley ◽  
...  
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Census Data ◽  
Dicentric Chromosome ◽  
Automated Assignment ◽  
High Yield ◽  
Radiation Incident ◽  
Accurate Dose ◽  
Population Scale ◽  
Us Census

AbstractIntroductionThe dicentric chromosome (DC) assay accurately quantifies exposure to radiation, however manual and semi-automated assignment of DCs has limited its use for a potential large-scale radiation incident. The Automated Dicentric Chromosome Identifier and Dose Estimator Chromosome (ADCI) software automates unattended DC detection and determines radiation exposures, fulfilling IAEA criteria for triage biodosimetry. We present high performance ADCI (ADCI-HT), with the requisite throughput to stratify exposures of populations in large scale radiation events.MethodsADCI-HT streamlines dose estimation by optimal scheduling of DC detection, given that the numbers of samples and metaphase cell images in each sample vary. A supercomputer analyzes these data in parallel, with each processor handling a single image at a time. Processor resources are managed hierarchically to maximize a constant stream of sample and image analysis. Metaphase data from populations of individuals with clinically relevant radiation exposures after simulated large nuclear incidents were analyzed. Sample counts were derived from US Census data. Analysis times and exposures were quantified for 15 different scenarios.ResultsProcessing of metaphase images from 1,744 samples (500 images each) used 16,384 CPUs and was completed in 1hr 11min 23sec, with radiation dose of all samples determined in 32 sec with 1,024 CPUs. Processing of 40,000 samples with varying numbers of metaphase cells, 10 different exposures from 5 different biodosimetry labs met IAEA accuracy criteria (dose estimate differences were < 0.5 Gy; median = 0.07) and was completed in ~25 hours. Population-scale metaphase image datasets within radiation contours of nuclear incidents were defined by exposure levels (either >1 Gy or >2 Gy). The time needed to analyze samples of all individuals receiving exposures from a high yield airborne nuclear device ranged from 0.6-7.4 days, depending on the population density.ConclusionADCI-HT delivers timely and accurate dose estimates in a simulated population-scale radiation incident.

scholarly journals RGCA: a Reliable GPU Cluster Architecture for Large-Scale Internet of Things Computing Based on Effective Performance-Energy Optimization

2017 ◽  
Author(s):  
Yuling Fang ◽  
Qingkui Chen ◽  
Neal N. Xiong ◽  
Deyu Zhao ◽  
Jingjuan Wang
Keyword(s):  
Energy Consumption ◽  
Internet Of Things ◽  
High Performance ◽  
Large Scale ◽  
High Reliability ◽  
Low Cost ◽  
Computing System ◽  
Gpu Cluster ◽  
Cluster Architecture ◽  
Level Parallelism

This paper aims to develop a low-cost, high-performance and high-reliability computing system to process large-scale data using common data mining algorithms in the Internet of Things computing. Considering the characteristics of IoT data processing, similar to mainstream high performance computing, we use a GPU cluster to achieve better IoT services. Firstly, we present an energy consumption calculation method (ECCM) based on WSN. Then, using the CUDA Programming model, we propose a Two-level Parallel Optimization Model (TLPOM) which exploits reasonable resource planning and common compiler optimization techniques to obtain the best blocks and threads configuration considering the resource constraints of each node. The key to this part is dynamic coupling Thread-Level Parallelism (TLP) and Instruction-Level Parallelism (ILP) to improve the performance of the algorithms without additional energy consumption. Finally, combining the ECCM and the TLPOM, we use the Reliable GPU Cluster Architecture (RGCA) to obtain a high-reliability computing system considering the nodes&rsquo; diversity, algorithm characteristics, etc. The results show that the performance of the algorithms significantly increased by 34.1%, 33.96% and 24.07% for Fermi, Kepler and Maxwell on average with TLPOM and the RGCA ensures that our IoT computing system provides low-cost and high-reliability services.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

High Performance Conductive Adhesives for Lead-Free Interconnects

2006 ◽  
Vol 968 ◽  
Author(s):  
Yi Li ◽  
ChingPing Wong
Keyword(s):  
High Power ◽  
High Performance ◽  
High Current Density ◽  
High Reliability ◽  
Nano Particles ◽  
Electrical Performance ◽  
Conductive Adhesives ◽  
Molecular Monolayers ◽  
Fine Pitch ◽  
Novel Approach

ABSTRACTTin-lead solder alloys are widely used in the electronic industry. With the recognition of toxicity of lead, however, electrically conductive adhesives (ECAs) have been considered as one of the most promising alternatives of tin-lead solder. While silver is the most widely used conductive fillers for ECA, silver migration has been the major concern for the high power and fine pitch applications. In this paper, a novel approach of using self-assembled monolayers (SAMs) passivation has been introduced to control the silver migration in nano-Ag ECAs. The protection of silver nano particles with SAMs reduced the silver migration dramatically and no migration was observed upon application of high voltages (up to 500 V) due to the formation of surface chelating compounds between the SAM and nano silver fillers. Unlike other migration control approaches which sacrifice electrical performance, the SAM passivated nano Ag fillers also enhanced the electrical conductivity and current carrying capability of adhesive joints significantly due to the improved interfacial properties and high current density of those molecular monolayers. The joint resistance of the SAM incorporated nano-Ag conductive adhesive could be achieved as low as 10−5 Ohm (the contact area is 100 ×100 μm2) and the maximum allowable current was higher than 3500 mA. As such, a fine pitch, high performance, non-migration and high reliability adhesives are developed for potential solder replacement in high voltage, high power device applications.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

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