Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000930-000959
Author(s):  
Wael Zohni ◽  
Rajesh Katkar ◽  
Rey Co ◽  
Rizza Cizek
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Volume ◽  
Third Party ◽  
High Yield ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Manufacturing Readiness

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

Manufacturing Readiness of BVA™ Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (1) ◽  
pp. 000024-000030 ◽  
Author(s):  
Rajesh Katkar ◽  
Rey Co ◽  
Wael Zohni
Keyword(s):  
Aspect Ratio ◽  
Smart Phone ◽  
Cost Effective ◽  
High Volume ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
Vertical Interconnects ◽  
Reliability Performance ◽  
Manufacturing Readiness

Ever increasing performance demands in a rapidly evolving smart phone market have led to a need for higher density interconnections linking memory components with logic devices in a standard package on package (PoP) configuration. While existing solutions present a technological roadblock at 350–400μm PoP pitch, new Bond Via Array (BVA™) technology provides a cost effective and scalable alternative that can achieve 240μm and below pitch values while utilizing conventional wirebond package assembly processes and tools. BVA is a high density, ultra-fine pitch package-on-package (PoP) interconnect solution that enables more than 1000 high aspect ratio connections between memory and processor components in a standard outline PoP. This increase significantly improves PoP capability and correspondingly provides increased bandwidth for the next generation of mobile devices. Here we discuss the 1020 IO BVA demonstration test vehicle, associated manufacturing process details, reliability performance and bi-level socket hardware developed to test these wire bond based novel interconnects. Furthermore the overall high volume manufacturing (HVM) readiness state of this technology for PoP applications will be described. The 1020 IO BVA prototype features 5 rows of vertical interconnects at 0.24mm pitch within an industry standard 14 x14mm package footprint. Although BVA interconnects were primarily developed for PoP packages, they offer many benefits over traditional vertical interconnects and can be implemented in a variety of other applications.

Angara interconnect makes GPU-based Desmos supercomputer an efficient tool for molecular dynamics calculations

2019 ◽  
Vol 33 (3) ◽  
pp. 507-521 ◽  
Author(s):  
Vladimir Stegailov ◽  
Ekaterina Dlinnova ◽  
Timur Ismagilov ◽  
Mikhail Khalilov ◽  
Nikolay Kondratyuk ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
Message Passing ◽  
High Performance ◽  
Message Passing Interface ◽  
Job Scheduling ◽  
Cost Effective ◽  
Test Bed ◽  
Molecular Dynamics Calculations ◽  
High Bandwidth ◽  
Network Topologies

In this article, we describe the Desmos supercomputer that consists of 32 hybrid nodes connected by a low-latency high-bandwidth Angara interconnect with torus topology. This supercomputer is aimed at cost-effective classical molecular dynamics calculations. Desmos serves as a test bed for the Angara interconnect that supports 3-D and 4-D torus network topologies and verifies its ability to unite massively parallel programming systems speeding-up effectively message-passing interface (MPI)-based applications. We describe the Angara interconnect presenting typical MPI benchmarks. Desmos benchmarks results for GROMACS, LAMMPS, VASP and CP2K are compared with the data for other high-performance computing (HPC) systems. Also, we consider the job scheduling statistics for several months of Desmos deployment.

scholarly journals Mg-Li Hybrid Batteries: The Combination of Fast Kinetics and Reduced Overpotential

2022 ◽  
Vol 2022 ◽  
pp. 1-18
Author(s):  
Yajie Li ◽  
Yongjian Zheng ◽  
Kai Guo ◽  
Jingtai Zhao ◽  
Chilin Li
Keyword(s):  
High Performance ◽  
Specific Capacity ◽  
Lithium Ion ◽  
Cost Effective ◽  
Material Design ◽  
High Volume ◽  
Future Research ◽  
Fast Kinetics ◽  
Interface Modification ◽  
Further Development

It is imperative for the development of cost-effective and high-performance batteries. Currently, lithium-ion batteries still occupy most of the market. However, limited lithium (Li) resource and energy density retard their further development. The magnesium (Mg) metal has several significant advantages; those make it a viable alternative to Li as anode, including high volume specific capacity and dendrite-free plating during cycling and high abundance. The Mg-Li hybrid batteries can combine the advantages of Li ion and Mg metal to achieve fast electrode kinetics and smooth anode deposition morphology. This review summarizes recent progresses in cathode material design and anode interface modification for Mg-Li hybrid batteries. We aim to illustrate the contribution of Li+ to the electrochemical performance improvement at both cathode and anode sides and to provide inspiration for the future research in this field.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2015 ◽  
Vol 2015 (1) ◽  
pp. 000822-000826 ◽  
Author(s):  
Won Kyoung Choi ◽  
Duk Ju Na ◽  
Kyaw Oo Aung ◽  
Andy Yong ◽  
Jaesik Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Process Development ◽  
Cost Effective ◽  
Access Point ◽  
Data Access ◽  
Memory Device ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2μm line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Understanding the Effects of Process Parameters to Compensate for Substrate Warpage in Chip on Flex (CoF) Assembly Using Conventional Reflow

2019 ◽  
Vol 2019 (1) ◽  
pp. 000428-000433
Author(s):  
Varun Soman ◽  
Vikram Venkatadri ◽  
Mark D. Poliks
Keyword(s):  
Substrate Surface ◽  
Cost Effective ◽  
High Volume ◽  
High Yield ◽  
Solder Paste ◽  
Conductive Adhesives ◽  
Process Yield ◽  
Aperture Diameter ◽  
Solder Balls ◽  
Aperture Opening

Abstract Mounting rigid silicon (Si) die on a flex substrate presents a unique set of challenges. Substrate surface flatness and warpage of the flex substrate before and during thermal processing being two of the biggest issues. Various processes such as thermocompression bonding using anisotropic conductive films and thermosonic bonding using non-conductive adhesives have been shown to be effective for chip on flex (CoF) applications. However, these processes sacrifice process throughput and are less cost effective. Hence these methods may not be suitable for high volume manufacturing (HVM). For this reason, a process that is suitable for HVM and uses standard reflow processes and equipment is highly desirable. This works presents preliminary results for such a CoF process that uses a simple fixture and standard processes, materials and equipment. CoF process for Si die using two types of interconnects, solder balls or Cu pillars, was developed. Solder paste was stencil printed before pick and place of the Si die to offset the lack of flex substrate flatness and substrate warpage. The effect of stencil aperture diameter and placement force on process yield and stand-off height was studied. It was demonstrated that high yield can be obtained with a process that uses wider stencil aperture opening for both type of interconnects investigated. It was also observed that the placement force did not have any effect on process yield or stand-off height. The process can also be easily scaled up for HVM.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Vacuum Packaging for High-Performance Low Cost MEMS Gyro Used in 6 Degree of Freedom Inertial Navigation System (DOF INS)

2011 ◽  
Vol 2011 (1) ◽  
pp. 000627-000634
Author(s):  
D. DeRoo ◽  
K. Shcheglov ◽  
M. Inbar ◽  
D. Smukowski ◽  
P. Zappella ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
High Vacuum ◽  
High Volume ◽  
High Yield ◽  
Test Results ◽  
Batch Fabrication ◽  
Mems Gyroscopes ◽  
Commercial Applications ◽  
The Military

Sensors in Motion Inc. is developing a navigation grade 6 DOF MEMS INS using its proprietary and patented technologies. The military is investing in INS and IMU technology which can answer its needs as well as provide the baseline for hundreds of other DOD and commercial applications which need a C-swap sensitive utility. SIM’s technology for MEMS gyros was conceived to address past problems associated with MEMS gyroscopes while leveraging the C-swap benefits of high volume, high yield batch fabrication, automated packaging, self-calibration, and thermal compensation. A key requirement for the MEMS Gyroscope is controlled vacuum-levels to obtain high Q devices. Gyro die are packaged using a multilayer package and getter system, which provides and maintains sealed vacuum cavities. Die are assembled into the LCC package using conventional assembly techniques and the package cavity is sealed using an SST 3150 high-vacuum sealing system. The SST system is used to activate a thin-film getter layer on the package lid before reflow of the solder seal. Resulting pressure levels have been determined by characterizing packaged but unlidded sensor die in a vacuum chamber. The package material, process flow and test results are summarized and reviewed. Tooling, process parameters, and test techniques are explained.

Methods to Reduce the Hierarchy of Interconnections in Electronic System

2020 ◽  
Vol 2020 (1) ◽  
pp. 000156-000159
Author(s):  
Dyi-Chung Hu ◽  
James Ho
Keyword(s):  
High Performance ◽  
Electronic System ◽  
Autonomous Driving ◽  
Computing System ◽  
Fine Pitch ◽  
Size Limitation ◽  
High Performance Computing System ◽  
High Bandwidth ◽  
The Cost ◽  
Structure Enhancement

Abstract In the era of AI, 5G, big data, and autonomous driving, those applications all require a high bandwidth low latency data computing. Traditional electronic packaging structures are classified into many levels and each level are connected by solders or cables. These many levels of structures cause system performance degradation. Hence structure solutions of 2.5D, 2.1D, 2.3D and 2.0D with multi-chip packaging are needed for high performance computing system. Currently 2.5D is the HPC standard structure, however the cost and size limitation of 2.5D drive users to seek alternative solutions. The structure of 2.0D, 2.1D and 2.3D offer less solder and TXVs are emerging as contenders to fill the requirement of large substrate size and fine line requirements in the future. Among them 2.0D structure shows great potential. Three 2.0D test vehicles have been built to evaluate fine pitch assembly, reliability and structure enhancement. The results show 2.0D structure has great potential to be a HPC solution of the near future.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

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