Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Electrical Performance Comparison between fcBGA and eWLB Packages

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000526-000544
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Gwang. Kim ◽  
...  
Keyword(s):  
Transmission Line ◽  
Cross Talk ◽  
Unit Length ◽  
Electrical Performance ◽  
Metal Loss ◽  
Wafer Level ◽  
Design Rules ◽  
Passivation Layers ◽  
The Cross ◽  
Metal Layers

Wafer-level packages, such as embedded-Wafer-Level-Ball-Grid-Array (eWLB) packages, can provide smaller form-factors and thinner profiles, as finer design rules on W/S, and thinner layers (both metal layers and passivation layers) can be applied in such packages. However, a routine conversion from fcBGA to eWLB does not guarantee the electrical performance will be the same. Designer's electrical skills still play important roles to reduce design cycle-time for meeting critical electrical performance. We compare the performance from typical fcBGA and eWLB packages in the following areas: insertion-loss for signal nets, power-ground impedance for P/G nets, and cross-talk for both signal nets and P/G nets. Simulation data for both fcBGA and eWLB, along with some experimental data, is provides in the paper. As metal-layer thickness (4um-12um) in eWLB is typically smaller, and finer design rules are used, the cross-section of a signal trace is smaller, which translates a higher metal-loss in unit- length. In addition, as the passivation layers in eWLB have slightly worse loss-tangent properties, it's substrate-loss is also little higher. The overall aspects above result in higher transmission-line (TML) loss in eWLB in unit-length. But as shorter trace-routing is possible in eWLB, given finer design rules, the overall transmission-line loss could be equivalent to that of a fcBGA transmission-line. The finer design rules on vias in eWLB facilitate to implement Power/Ground (P/G) planes in a more continuous way, and contribute to less P/G impedance. In addition, as the layer-to-layer separation is smaller, decoupling capacitance inheritably made between the P/G planes is larger, which eventually helps to provide a better or smaller P/G loop-impedance. Because of less separation distance between metal layers in eWLB, the signal traces see much closer GND planes (e.g., 5um in eWLB versus 50um in fcBGA) in their proximities. The closer GND planes make the electrical fields more locally contained. As a result, in a typical eWLB design (e.g., 12um/12um for L/S), the cross-talk between DDR data buses is typically smaller than that from a fcBGA design (e.g., 30um/30um for L/S).

Method of Recovering SEM Inspection Induced MOSFETs Degradation before Electrical Characterization

2016 ◽  
Author(s):  
Qi Lin ◽  
Hans Pan ◽  
Jonathan Chang ◽  
Rung-Jiun Lin ◽  
Shih-Hsin Chang ◽  
...  
Keyword(s):  
Exposure Time ◽  
Positive Charge ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Uv Curing ◽  
Gate Oxide ◽  
Uv Exposure ◽  
Electrical Performance ◽  
Technology Scaling ◽  
Curing Methods

Abstract With technology scaling, semiconductor devices have become more prone to damage induced by SEM inspection. In this work, we find that today’s widely-used 0.5KeV SEM can also alter the electrical performance of the devices at 20nm technology node. Vts shift with SEM exposure time on nMOS and pMOS has been studied extensively. The cause of the degradation is the positive charge trapped in the gate oxide during SEM radiation. A conventional UV_eraser for EPROM was applied to SEM-damaged devices. The measurement data show that UV exposure can cure most of SEM-induced damage. In the future, if a regular SEM inspection is followed by nanoprobing device characterization, UV curing or another curing methods is required to recover the electric characteristics of the device before nanoprobing.

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Power Efficiency ◽  
High Performance ◽  
Electrical Characterization ◽  
Cost Effective ◽  
Electrical Performance ◽  
Wearable Electronics ◽  
Wafer Level ◽  
Low Profile ◽  
Line Spacing

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

Material and Process Developments for Robust and High Reliability Glass Wafers for 2.5D Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001364-001377
Author(s):  
Roupen Keusseyan ◽  
Tim Mobley
Keyword(s):  
Borosilicate Glass ◽  
High Speed ◽  
High Reliability ◽  
Electrical Performance ◽  
Next Generation ◽  
Wafer Level ◽  
Hole Formation ◽  
Heterogeneous Devices ◽  
Primary Key ◽  
Through Hole

Borosilicate glass based wafer technologies are being developed for next generation high speed electronic, telecom and biotech systems; that integrate heterogeneous devices in a single package for improved electrical performance. The primary key to success is to have a well understood via through the glass that can be used as a core to build wafer level packages from. The present paper will discuss developments in through hole formation technology and via metallization materials and processes. Through hole formation in borosilicate glass with corresponding wall morphology and chemistry play important roles in building robust vias through the glass. These hole characteristics and their dependence on performance, defects at the wafer level and key developments that have been achieved to overcome them will be discussed in detail.

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