Electrical Performance Comparison between fcBGA and eWLB Packages

Wafer-level packages, such as embedded-Wafer-Level-Ball-Grid-Array (eWLB) packages, can provide smaller form-factors and thinner profiles, as finer design rules on W/S, and thinner layers (both metal layers and passivation layers) can be applied in such packages. However, a routine conversion from fcBGA to eWLB does not guarantee the electrical performance will be the same. Designer's electrical skills still play important roles to reduce design cycle-time for meeting critical electrical performance. We compare the performance from typical fcBGA and eWLB packages in the following areas: insertion-loss for signal nets, power-ground impedance for P/G nets, and cross-talk for both signal nets and P/G nets. Simulation data for both fcBGA and eWLB, along with some experimental data, is provides in the paper. As metal-layer thickness (4um-12um) in eWLB is typically smaller, and finer design rules are used, the cross-section of a signal trace is smaller, which translates a higher metal-loss in unit- length. In addition, as the passivation layers in eWLB have slightly worse loss-tangent properties, it's substrate-loss is also little higher. The overall aspects above result in higher transmission-line (TML) loss in eWLB in unit-length. But as shorter trace-routing is possible in eWLB, given finer design rules, the overall transmission-line loss could be equivalent to that of a fcBGA transmission-line. The finer design rules on vias in eWLB facilitate to implement Power/Ground (P/G) planes in a more continuous way, and contribute to less P/G impedance. In addition, as the layer-to-layer separation is smaller, decoupling capacitance inheritably made between the P/G planes is larger, which eventually helps to provide a better or smaller P/G loop-impedance. Because of less separation distance between metal layers in eWLB, the signal traces see much closer GND planes (e.g., 5um in eWLB versus 50um in fcBGA) in their proximities. The closer GND planes make the electrical fields more locally contained. As a result, in a typical eWLB design (e.g., 12um/12um for L/S), the cross-talk between DDR data buses is typically smaller than that from a fcBGA design (e.g., 30um/30um for L/S).