Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000441-000454
Author(s):  
Siddharth Bhopte ◽  
Jesse Galloway ◽  
Kyung-Rok Park ◽  
Hyun-Jin Park ◽  
Jeong-Han Choi ◽  
...  
Keyword(s):  
Flip Chip ◽  
Computational Study ◽  
Heating Temperature ◽  
Form Factors ◽  
Temperature Gradients ◽  
Electrical Performance ◽  
Large Temperature ◽  
Compression Load ◽  
Chip Technology ◽  
Fine Pitch

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (<60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

Flip Chip Fine Pitch PBGA Yield Study

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001829-001856
Author(s):  
Tim Pham ◽  
Betty Yeung ◽  
Trent Uehling ◽  
Brett Wilkerson
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Simulations ◽  
Flip Chip ◽  
Yield Loss ◽  
Combined Effect ◽  
Electrical Performance ◽  
Design Parameters ◽  
Surface Evolver ◽  
Solidification Temperature ◽  
Fine Pitch

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.

The effect of underfill on thermal stresses on logic ASIC and its electrical performance

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Babak Talebanpour ◽  
Doug Link
Keyword(s):  
Frequency Shift ◽  
Flip Chip ◽  
Thermal Stresses ◽  
Electrical Performance ◽  
Shear Stresses ◽  
Normal Stresses ◽  
Clock Frequency ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Reflow

Flip chip technology is widely used today to support the demand for high interconnect density of modern microelectronic circuits. Conventionally, solder bumps have provided the electrical and mechanical connection between the chip and the substrate. The solder bumps are prone to fatigue and failure especially in large chips and/or mobile devices. Conventional underfilling process which consists of flowing an epoxy under the chip and curing it after the flip chip connections are made mechanically supports the assembly, significantly reducing the shear stresses on the bumps and minimizing the chip warpage due to thermal stresses. However, underfill also has side effects. The flow of underfill depends on a lot of parameters usually can be incomplete or containing a lot of voids, inconsistent underfill results in unpredictable overall durability or manufacturing survivability. Furthermore, underfilling introduces certain components of stress, this form of stress can have adverse effect on the electrical performance of the die if it occurs close to stress sensitive parts. In this study, the effect of underfilling and its quality on the clock frequency shift of a DSP (Digital Signal Processor) chip used by Starkey Hearing Technologies is investigated. Clock frequency measurements after a solder reflow process has been compared for different underfill materials, and underfill quality. Finite element analysis was implemented to assess the stress transferred to the clock circuit on the die and examine how existence of underfill, bump height, location of bumps, and underfill voids affect the stress. The following results have been concluded based on the work presented in this paper:The conventional underfilling process for dies with very small standoff heights can be very in consistent, strongly depending on the gap uniformity, flex traces, cleanliness of the package after solder reflow, etc. large percentage of delamination and voids can occur. The voids and delamination can cause solder extrusion as well as inconsistent stress distribution on the die.Although underfilling causes large normal stresses on the die, it reduces the effective stress on the die which can translate to less warpage and the problems associated with it.The height of the bumps does not strongly affect the amount of stress build up on the die if it does not compromise a uniform underfill.Relocation of the bumps away from the clock circuit significantly reduces the stress on the clock, and it has been shown to minimize the clock shift in practice. A minimum amount of distance between the clock circuit and solder bumps should be considered when DSP layout are designed.If the clock circuit surface is not in contact with the underfill, normal stresses will not be transferred to the clock circuit minimizing the clock frequency shift. The best approach to implement this method is wafer-level underfill technique. The underfill will be applied at the wafer fab and precision lasers can cut the underfill laminate at desired locations. This process can guarantee support for the die by a uniform underfill, while stress sensitive parts will be protected against unwanted thermal stresses.

Fine pitch low-cost bumping for flip chip technology

2003 ◽  
Author(s):  
Szu-Wei Lu ◽  
Ruoh-Huey Uang ◽  
Kuo-Chuan Chen ◽  
Hsu-Tien Hu ◽  
Ling-Chen Kung ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Chip Technology ◽  
Fine Pitch

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology

1998 ◽  
Vol 21 (1) ◽  
pp. 41-50 ◽  
Author(s):  
J. Kloeser ◽  
K. Heinricht ◽  
K. Kutzner ◽  
E. Jung ◽  
A. Ostmann ◽  
...  
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Stencil Printing ◽  
Chip Technology ◽  
Fine Pitch ◽  
Lead Free Solders
Sign in / Sign up

Export Citation Format

Share Document