Laddered-UBM Structure: Bump Reliability Improvement through Distribution of Load Concentration Points

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001827-001839
Author(s):  
Roden Topacio
Keyword(s):  
Load Distribution ◽  
Flip Chip ◽  
Solder Bump ◽  
Dielectric Film ◽  
Coefficient Of Thermal Expansion ◽  
Circuit Board ◽  
Bending Moments ◽  
Semiconductor Chip ◽  
Semiconductor Chips ◽  
Solidification Stage

Flip-chip mounting schemes have been used for decades to mount semiconductor chips to substrates. In flip-chip process, a solder bump is metallurgically bonded to the under-bump-metallurgy, also known as UBM, on a given pad of the semiconductor chip and a pre-solder is metallurgically bonded to a corresponding pad of the substrate. Thereafter the solder bump and the pre-solder are brought into proximity and metallurgically bonded using reflow. Flip-chip solder joints are subjected to mechanical stresses from a variety of sources, such as coefficient of thermal expansion mismatches, ductility differences and circuit board warping. Such stresses can subject the conventional UBM structure to bending moments specially during the flip-chip reflow solder solidification stage where the bump is still unprotected by the underfill. The effect is somewhat directional in that the stresses tend to be greatest nearer the die edges and corners and fall off with increasing proximity to the die center. The bending moments associated with this so-called edge effect can impose stresses on the dielectric film beneath the UBM structure that, if large enough, can produce fracture. This paper will discuss the load distribution on a conventional UBM structure due to the bending moments and how the Laddered-UBM structure attempts to overcome or reduce the effects of these bending moments. Contrary to conventional methods where stress concentration points are eliminated, the Laddered-UBM is designed to strategically increase the number of load concentration points along the UBM structure. With the increased number of load concentration points, the stress along the UBM is distributed more evenly which effectively reduces the stress at any given point thus preventing a single large enough stress to cause dielectric fracture. Theoretical analysis and experimental data including reliability results on both the conventional UBM structure and the Laddered-UBM structure will be presented and discussed in this paper.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000737-000758 ◽  
Author(s):  
Craig D. Hillman ◽  
Randy Schueller ◽  
Greg Caswell
Keyword(s):  
Finite Element ◽  
Tensile Stress ◽  
Finite Element Modeling ◽  
Flip Chip ◽  
Solder Bump ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Conditions ◽  
Temperature Dependent ◽  
Element Modeling ◽  
Stress States

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling. The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.

An Yield Model for Electronics Assembly

2005 ◽  
Author(s):  
N. Gnanasambandam ◽  
M. Munikrishnan ◽  
V. Poyyapakkam ◽  
P. Borgesen ◽  
K. Srihari
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Bump ◽  
Circuit Board ◽  
Design Stage ◽  
Manufacturing Cost ◽  
Electronic Components ◽  
Yield Model ◽  
Printed Circuit ◽  
Pcb Assembly

Managing assembly yield in the Printed Circuit Board (PCB) assembly process is crucial in reducing the overall manufacturing cost of a product. Being faced with electronic components that have high interconnect (pin or solder bump) count, density, and complexity, it is extremely important to streamline the manufacturing losses arising from misplaced or poorly assembled components. In order to achieve this goal, yield models are utilized to anticipate and evaluate problems and their causes. This activity could be potentially implemented at the design stage or at least much before the product reaches the manufacturing floor. This research examines some important factors that affect area array (BGA, CSP, flip chip) assembly yields, taking a two-pronged approach to modeling. Achievable yield is classified into placement and assembly components and is estimated using a simulation model.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Numerical Analysis on Thermal Deformation of Linear Motor in Chip Mounter

2011 ◽  
Author(s):  
Kang-Woo Joo ◽  
Kwang-Sun Kim ◽  
Jun-Young Kim ◽  
Hee-Rak Beom
Keyword(s):  
Thermal Deformation ◽  
Linear Motor ◽  
Ball Screw ◽  
Heat Transfer Analysis ◽  
Semiconductor Chip ◽  
Research Activities ◽  
And Performance ◽  
Stress And Deformation ◽  
Electro Magnetic ◽  
Semiconductor Chips

In the semiconductor chip mounting process, the size of semiconductor chips is decreasing, while the number of mounting the chips per time are increasing, and this trend is being accelerated. The research activities to develop the chip mounters, which are able to mount rapidly and accurately, have been needed in the industry. With this background, the linear motor in the chip mounters has been an important part. The electro-magnetic type linear motor has many advantages such as direct linear reciprocating motion being compared with the rotary motor and the ball screw type linear motor. However, the electro-magnetic linear motor has thermal problems. These problems affect life and performance of motor and bring out the other problems such as thermal stress and deformation. The heat transfer analysis is difficult to solve thermal problems because the moving and fixed parts coexist. The trial & error methods have been therefore used under majority of cases. In this paper, we investigated the thermal deformation problems of linear motor in a chip mounter and the optimized parameters to design the motion parts of electro-magnetic linear motor were obtained.

Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Precise Quantitative Evaluation of Nano-Ordered Intermetallic Compounds in Sn-3.0Ag-0.5Cu Lead-Free Solder Bump by Using TEM

2008 ◽  
Vol 47-50 ◽  
pp. 907-911
Author(s):  
Chang Woo Lee ◽  
Y.S. Shin ◽  
J.H. Kim
Keyword(s):  
Intermetallic Compounds ◽  
Flip Chip ◽  
Solder Bump ◽  
Lead Free Solder ◽  
Growth Behaviour ◽  
Sic Particles ◽  
Imcs Growth ◽  
Ordered Intermetallic ◽  
Free Solder ◽  
The One

The growth behaviour of the intermetallic compounds (IMCs) in Pb-free solder bump is investigated. The Pb-free micro-bump, Sn-50%Bi, was fabricated by binary electroplating for flip-chip bond. The diameter of the bump is about 506m and the height is about 60 6m. In order to increase the reliability of the bonding, it is necessary to protect the growth of the IMCs in interface between Cu pad and the solder bump. For control of IMCs growth, SiC particles were distributed in the micro-solder bump during electroplating. The thickness of the IMCs in the interface was estimated by FE-SEM, EDS, XRF and TEM. From the results, The IMCs were found as Cu6Sn5 and Cu3Sn. The thickness of the IMCs decreases with increase the amount of SiC particles until 4 g/cm2. The one candidate of the reasons is that the SiC particles could decrease the area which be reacted between the solder and Cu layer. And another candidate is that the particle can make to difficult inter-diffusion within the interface.

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